|
|
PDF NCN6001 Data sheet ( Hoja de datos )
| Número de pieza | NCN6001 | |
| Descripción | Compact Smart Card Interface IC | |
| Fabricantes | ON | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de NCN6001 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
NCN6001
Compact Smart Card
Interface IC
The NCN6001 is an integrated circuit dedicated to the smart card
interface applications. The device handles any type of smart card
through a simple and flexible microcontroller interface. On top of that,
thanks to the built−in chip select pin, several couplers can be
connected in parallel.
The device is particularly suited for low cost, low power
applications, with high extended battery life coming from extremely
low quiescent current.
Features
• 100% Compatible with ISO 7816−3, EMV and GIE−CB Standards
• Fully GSM Compliant
• Wide Battery Supply Voltage Range: 2.7 < VCC < 5.5 V
• Programmable CRD_VCC Supply Handles 1.8 V, 3.0 V or 5.0 V
Card Operation
• Programmable Rise and Fall Card Clock Slopes
• Programmable Card Clock Divider
• Built−in Chip Select Logic Allows Parallel Coupling Operation
• ESD Protection on Card Pins (8.0 kV, Human Body Model)
• Supports up to 40 MHz Input Clock
• Built−in Programmable CRD_CLK Stop Function Handles Run or
Low State
• Programmable CRD_CLK Slopes to Cope with Wide Operating
Frequency Range
• Fast CRD_VCC Turn−on and Turn−off Sequence
• These are Pb−Free Devices
Typical Applications
• E−Commerce Interface
• Automatic Teller Machine (ATM) Smart Card
• Point of Sales (POS) System
• Pay TV System
www.onsemi.com
1
TSSOP−20
DTB SUFFIX
CASE 948E
PIN CONNECTIONS
I/O 1
INT 2
CLK_IN 3
MOSI 4
CLK_SPI 5
EN_RPU 6
MISO 7
CS 8
VCC 9
Lout_L 10
(Top View)
20 CRD_IO
19 CRD_RST
18 CRD_DET
17 CRD_CLK
16 GND
15 C4/S0
14 C8/S1
13 CRD_VCC
12 Lout_H
11 PWR_GND
MARKING DIAGRAM
20
NCN
6001
ALYWG
G
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 32 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
October, 2014 − Rev. 6
1
Publication Order Number:
NCN6001/D
1 page  
NCN6001
PIN FUNCTIONS AND DESCRIPTION (continued)
TSSOP Name
18 CRD_DET
Type
INPUT
Description
The signal coming from the external card connector is used to detect the presence of the card.
A built−in pullup low current source biases this pin High, making it active LOW, assuming one
side of the external switch is connected to ground. A built−in digital filter protect the system
against voltage spikes present on this pin.
The polarity of the signal is programmable by the MOSI message, according to the logic state
depicted Table 2. On the other hand, the meaning of the feedback message contained in the
MISO register bit b4, depends upon the SPI mode of operation as defined here below:
SPI Normal Mode: The MISO bit b4 is High when a card is inserted, whatever be the polarity
of the card detect switch.
SPI Special Mode: The MISO bit b4 copies the logic state of the Card detect switch as
depicted here below, whatever be the polarity of the switch used to handle the detection:
CRD_DET = Low → MISO/b4 = Low
CRD_DET = High → MISO/b4 = High
In both cases, the chip must be programmed to control the right logic state (Table 2).
Since the bias current supplied by the chip is very low, typically 5.0 mA, care must be observed
to avoid low impedance or cross coupling when this pin is in the Open state.
19 CRD_RST OUTPUT This pin is connected to the RESET pin of the card connector. A level translator adapts the
RESET signal from the microcontroller to the external card. The output current is internally
limited to 15 mA.
The CRD_RST is validated when CS = Low and hard wired to Ground when the card is
deactivated, by and internal active pull down circuit.
Care must be observed, at PCB design level, to avoid cross coupling between this signal and
the CRD_CLK clock.
20 CRD_IO
I/O
Pullup
This pin handles the connection to the serial I/O pin of the card connector. A bidirectional level
translator adapts the serial I/O signal between the card and the microcontroller. An internal
active pull down MOS device forces this pin to Ground during either the CRD_VCC startup
sequence, or when CRD_VCC = 0 V. The CRD_IO pin current is internally limited to 15 mA.
Care must be observed, at PCB design level, to avoid cross coupling between this signal and
the CRD_CLK clock.
http://onsemi.com
5
5 Page 
NCN6001
Table 2. WRT_REG BITS DEFINITIONS AND FUNCTIONS
ADDRESS
PARAMETERS
CHIP
BANK
MOSI bits
[b3:b2]
1
b7 b6 b5
b4
b3 b2 b1 b0
CRD_CLK
1 0 X X RST 0 0 0 0 Low
1 0 X X RST 0 1 0 1
1/1
1 0 X X RST 1 0 1 0
1/2
1 0 X X RST 1 1 1 1
1/4
1
101
0
0 000
−
1
101
0
0 001
−
1
101
0
0 010
−
1
101
0
0 011
−
1
101
0
0 100
−
1
101
0
0 101
−
1
111
−
− −−−
−
2 1 0 0 RST 0 0 0 0 Low
2 1 0 0 RST 0 1 0 1
1/1
2 1 0 0 RST 1 0 1 0
1/2
2 1 0 0 RST 1 1 1 1
1/4
2 1 1 0 RST CLK I/O C4 C8
−
2
101
0
0 000
−
2
101
0
0 001
−
2
101
0
0 010
−
2
101
0
0 011
−
2
101
0
0 100
−
2
101
0
0 101
−
2
111
−
− −−−
−
11. Chip Bank 1 = Asynchronous cards, four slots addresses 1 to 4.
Chip Bank 2 = Asynchronous or synchronous card, single slot.
12. Address 101 and bits [b0 : b4] not documented in the table are reserved for future use.
Address 111 is reserved for future use.
MOSI bits
[b1:b0]
CRD_VCC
0
1.8 V
3.0 V
5.0 V
−
−
−
−
−
−
−
0
1.8 V
3.0 V
5.0 V
−
−
−
−
−
−
−
−
MOSI bits
[b7:b0]
CRD_DET
−
−
−
−
NO
NC
Special
Normal
SLO_SLP
FST_SLP
RFU
−
−
−
−
Data to Sync. Card
NO
NC
Special
Normal
SLO_SLP
FST_SLP
RFU
Although using the %111XXXXX code is harmless from
a NCN6001 silicon standpoint, care must be observed to
avoid uncontrolled operation of the interface sharing the
same digital bus. When this code is presented on the digital
bus, the CRD_RST signal of any interface sharing the CS
signal, immediately reflects the digital content of the MOSI
bit b4 register. Similarly, the MISO register of the shared
interface is presented on the SPI port. Consequently, data
collision, at MISO level, and uncontrolled card operation are
likely to happen if the system uses a common Chip Select
line. It is strongly recommended to run a dedicated CS bit to
any external circuit intended to use the $111xxxxx code.
On the other hand, the CRD_RST signal will be forced to
Low when the internal register of the chip is programmed to
accommodate different hardware conditions (NO/NC,
Special/Normal, SLO_SLP/FST_SLP). Generally speaking,
such a configuration shall take place during the Power On
Reset to avoid CRD_RST activation.
http://onsemi.com
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet NCN6001.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| NCN6000 | Compact Smart Card Interface IC |  ON Semiconductor |
| NCN6001 | Compact Smart Card Interface IC | ON |
| NCN6004A | Dual SAM/SIM Interface Integrated Circuit | ON |
| NCN6004AFTBR2 | Dual SAM/SIM Interface Integrated Circuit | ON |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |