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PDF N74F843D Data sheet ( Hoja de datos )
| Número de pieza | N74F843D | |
| Descripción | Bus interface latches | |
| Fabricantes | Philips | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de N74F843D (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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INTEGRATED CIRCUITS
74F841/842/843/845/846
Bus interface latches
Product specification
Replaces datasheet 74F841/842/843/844/845/846 of 1999 Jan 08
IC15 Data Handbook
1999 Jun 23
Philips
Semiconductors
1 page  
Philips Semiconductors
Bus interface latches
PIN CONFIGURATION for 74F845
OE0 1
OE1 2
D0 3
D1 4
D2 5
D3 6
D4 7
D5 8
D6 9
D7 10
MR 11
GND 12
24 VCC
23 OE2
22 Q0
21 Q1
20 Q2
19 Q3
18 Q4
17 Q5
16 Q6
15 Q7
14 PRE
13 LE
SF01291
LOGIC SYMBOL for 74F845
3 4 5 6 7 8 9 10
D0 D1 D2 D3 D4 D5 D6 D7
13 LE
14 PRE
11 MR
1 OE0
2 OE1
23 OE2
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
VCC = Pin 24
GND = Pin 12
22 21 20 19 18 17 16 15
SF01292
LOGIC SYMBOL (IEEE/IEC) for 74F845
1&
2 EN
23
14 S2
11
R
13
C1
3
1D
4
5
6
7
8
9
10
22
21
20
19
18
17
16
15
SF01293A
1999 Jun 23
Product specification
74F841/74F842/74F843/
74F845/74F846
PIN CONFIGURATION for 74F846
OE0 1
OE1 2
D0 3
D1 4
D2 5
D3 6
D4 7
D5 8
D6 9
D7 10
MR 11
GND 12
24 VCC
23 OE2
22 Q0
21 Q1
20 Q2
19 Q3
18 Q4
17 Q5
16 Q6
15 Q7
14 PRE
13 LE
SF01294
LOGIC SYMBOL for 74F846
3 4 5 6 7 8 9 10
D0 D1 D2 D3 D4 D5 D6 D7
13 LE
14 PRE
11 MR
1 OE0
2 OE1
23 OE2
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
VCC = Pin 24
GND = Pin 12
22 21 20 19 18 17 16 15
SF01295
LOGIC SYMBOL (IEEE/IEC) for 74F846
1&
2 EN
23
14
S2
11
R
13
C1
3
1D
4
5
6
7
8
9
10
22
21
20
19
18
17
16
15
SF01296A
5
5 Page 
Philips Semiconductors
Bus interface latches
Product specification
74F841/74F842/74F843/
74F845/74F846
AC ELECTRICAL CHARACTERISTICS for 74F841/74F842
SYMBOL
PARAMETER
TEST
CONDITION
tPLH Propagation delay
tPHL Dn to Qn
tPLH Propagation delay
tPHL LE to Qn
74F841
Waveform 1, 2
Waveform 1, 2
tPLH Propagation delay
tPHL Dn to Qn
tPLH Propagation delay
tPHL LE to Qn
74F842
Waveform 1, 2
Waveform 1, 2
tPZH
Output enable time
tPZL High or Low-level OEn to Qn or Qn
Waveform 5
Waveform 6
tPHZ
Output disable time
tPLZ High or Low-level OEn to Qn or Qn
Waveform 5
Waveform 6
LIMITS
Tamb = +25°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
MIN TYP MAX
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MIN MAX
2.0 4.0 7.5
2.5 4.5 7.5
2.0
2.5
8.0
8.0
4.5 6.5 9.5
4.0 6.0 9.0
4.0
3.5
10.0
9.5
3.5 5.5 8.5
3.0 5.0 8.0
4.5
4.0
9.0
8.5
5.0 7.0 10.0
4.5 6.5 9.0
3.0
3.0
10.5
9.5
2.5 4.5 8.0
4.0 6.0 9.5
2.0
3.0
8.5
10.5
1.0 4.5 8.0
1.0 5.0 8.0
1.0
1.0
8.5
8.5
UNIT
ns
ns
ns
ns
ns
ns
AC SETUP REQUIREMENTS for 74F841/74F842
SYMBOL
PARAMETER
TEST
CONDITION
ts(H)
ts(L)
th(H)
th(L)
tw(H)
th(H)
th(L)
tw(H)
Setup time, High or Low
Dn to LE
Hold time, High or Low
Dn to LE
LE pulse width, High
Hold time, High or Low
Dn to LE
LE pulse width, High
74F841
74F842
Waveform 4
Waveform 4
Waveform 4
Waveform 4
Waveform 4
LIMITS
Tamb = +25°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
MIN TYP
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MIN MAX
0.0 1.0
0.0 1.0
2.5 3.0
3.0 4.0
3.5 4.0
3.0 3.5
3.5 4.5
3.0 3.0
UNIT
ns
ns
ns
ns
ns
1999 Jun 23
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet N74F843D.PDF ] | |
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