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PDF N74F385N Data sheet ( Hoja de datos )
| Número de pieza | N74F385N | |
| Descripción | Quad serial adder/subtractor | |
| Fabricantes | Philips | |
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Philips Semiconductors
Quad serial adder/subtractor
Product specification
74F385
FEATURES
• Four independent adders/subtractors
• Two’s complement arithmetic
• Synchronous operation
• Common Clear and Clock
• 74F385 is designed for use with serial multipliers in implementing
digital filters and butterfly networks in fast Fourier transforms
DESCRIPTION
The 74F385 contains four independent adder/subtractor elements
with common Clock and Master Reset. Each adder/subtractor
contains a sum flop-flop and a carry flip-flop for synchronous
operations. Flip-flop state changes occur on the rising edge of the
Clock Pulse (CP) input signal. The Select (S) input should be Low
for the Add (A plus B) mode and High for the Subtract (A minus B)
mode. A Low signal on the asynchronous Master Reset (MR) input
clears the sum flip-flop and resets the Carry flip-flop to zero in the
Add mode or presets it to one in the Subtract mode.
PIN CONFIGURATION
CP 1
F0 2
S0 3
B0 4
A0 5
A1 6
B1 7
S1 8
F1 9
GND 10
TYPE
74F385
TYPICAL fMAX
140 MHz
20 VCC
19 F3
18 S3
17 B3
16 A3
15 A2
14 B2
13 S2
12 F2
11 MR
SF00928
TYPICAL SUPPLY
CURRENT (TOTAL)
55mA
ORDERING INFORMATION
DESCRIPTION
20-pin plastic DIP
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
N74F385N
20-pin plastic SO
N74F385D
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
A0 – A3
A operand inputs
B0 – B3
B operand inputs
S0 – S3
Function select inputs
CP Clock pulse input (active rising edge)
MR Asynchronous Master Reset input (active Low)
F0–F3
Sum or difference outputs
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
74F (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
1989 Sep 20
1 853–0868 97678
1 page  
Philips Semiconductors
Quad serial adder/subtractor
Product specification
74F385
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
fMAX
tPLH
tPHL
tPLH
Maximum clock frequency
Propagation delay,
Cn to Fn
Propagation delay, MR to Fn
AC SETUP REQUIREMENTS
SYMBOL
PARAMETER
ts (H)
ts (L)
th (H)
th (L)
ts (H)
ts (L)
tw (L)
tREC (L)
Setup time, High or Low
An, Bn or Sn to CP
Hold time, High or Low
An, Bn or Sn to CP
CP Pulse width
High or Low
MR Pulse width
Low
Recovery time
MR to CP
TEST
CONDITION
Waveform 1
Waveform 1
Waveform 2
LIMITS
Tamb = +25°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
MIN TYP MAX
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MIN MAX
105 140
90
3.0 5.0 8.0
3.5 5.5 9.0
2.5
3.5
9.0
10.0
4.0 6.5 9.5
4.0
10.5
UNIT
MHz
ns
ns
TEST
CONDITION
Waveform 3
Waveform 3
Waveform 2
Waveform 2
LIMITS
Tamb = +25°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MIN TYP MAX
MIN
MAX
12.0 12.0
12.0 12.0
00
00
6.0 6.0
6.0 6.0
UNIT
ns
ns
ns
6.0 6.0 ns
Waveform 2
8.5
9.5 ns
AC WAVEFORMS
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performances.
CP VM
1/fmax
tw(H)
tPHL
VM
tw(L)
VM
tPLH
MR VM
VM
tW (L)
tREC
CP VM
Fn VM
VM
SF00932
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
tPHL
Fn VM
Waveform 2. Master Reset Pulse Width,
Master Reset to Output Delay and
Master Reset to Clock Recovery Time
SF00933
An, Bn, Sn
VM VM
ts(H) th(H)
VM
ts(L)
VM
th(L)
CP VM
VM
SF00934
Waveform 3. Data and Select Setup and Hold Times
1989 Sep 20
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet N74F385N.PDF ] | |
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