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What is NTB90N02T4?

This electronic component, produced by the manufacturer "ON", performs the same function as "Power MOSFET 90 Amps / 24 Volts".


NTB90N02T4 Datasheet PDF - ON

Part Number NTB90N02T4
Description Power MOSFET 90 Amps / 24 Volts
Manufacturers ON 
Logo ON Logo 


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NTB90N02, NTP90N02
Power MOSFET
90 Amps, 24 Volts
N−Channel D2PAK and TO−220
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
Typical Applications
Power Supplies
Converters
Power Motor Controls
Bridge Circuits
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
− Continuous
VDSS
VGS
24
"20
Vdc
Vdc
Drain Current
− Continuous @ TA = 25°C
− Single Pulse (tp = 10 ms)
Total Power Dissipation @ TA = 25°C
Derate above 25°C
ID 90* A
IDM 200 A
PD 85 W
0.66 W/°C
Operating and Storage Temperature
TJ, Tstg
− 55
to
+150
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 28 Vdc, VGS = 10 Vdc, L = 5.0 mH,
IL(pk) = 17 A, RG = 25 W)
Thermal Resistance
Junction−to−Case
Junction−to−Ambient (Note 1)
EAS 733 mJ
RqJC
RqJA
°C/W
1.55
70
Maximum Lead Temperature for Soldering Pur- TL 260 °C
poses, 1/8from case for 10 seconds
1. When surface mounted to an FR4 board using 1pad size,
(Cu Area 1.127 in2).
2. When surface mounted to an FR4 board using minimum recommended pad
size, (Cu Area 0.412 in2).
*Chip current capability limited by package.
N−Channel
D
G
S
http://onsemi.com
V(BR)DSS
24 V
RDS(on) TYP
5.0 mW @ 10 V
7.5 mW @ 4.5 V
ID MAX
90 A
4
4
1
2
3
TO−220AB
CASE 221A
Style 5
12
3
D2PAK
CASE 418B
Style 2
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
NTx90N02
LLYWW
1
Gate
3
Source
NTx90N02
LLYWW
1
Gate
2
Drain
2
Drain
NTx90N02
x
LL
Y
WW
= Device Code
= P or B
=
=
=
LYWoeocararktiWoneCe3Skooduerce
ORDERING INFORMATION
Device
Package
Shipping
NTP90N02
NTB90N02
TO−220AB
D2PAK
50 Units/Rail
50 Units/Rail
NTB90N02T4
D2PAK
800/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2003
October, 2003 − Rev. 1
1
Publication Order Number:
NTB90N02/D

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NTB90N02T4 equivalent
NTB90N02, NTP90N02
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t + QńIG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr + Q2 R2ń10(VGG * VGSP)
tf + Q2 R2ńVGSP
where:
VGG = the gate drive voltage, which varies from
zero to VGG
RG = the gate drive resistance and Q2 and VGSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current
is not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network.
The equations are:
td(on) + RG Ciss In [VGGń(VGG * VGSP)]
td(off) + RG Ciss In (VGGńVGSP)
The capacitance (Ciss) is read from the capacitance curve
at a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.33
8.38
0.42
10.66
0.63
17.02
0.08
2.032
0.04
1.016
0.24
6.096
0.12
3.05
inches
mm
http://onsemi.com
5


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Part NumberDescriptionMFRS
NTB90N02T4The function is Power MOSFET 90 Amps / 24 Volts. ONON

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