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PDF NSBMC290-16 Data sheet ( Hoja de datos )
| Número de pieza | NSBMC290-16 | |
| Descripción | Burst Mode Memory Controller | |
| Fabricantes | National | |
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July 1993
NSBMC290TM-16 -20 -25 -33
Burst Mode Memory Controller
General Description
The NSBMC290 is functionally equivalent to the
V29BMCTM The NSBMC290 Burst Mode Memory Control-
ler is a single chip device designed to simplify the imple-
mentation of burst mode access in high performance sys-
tems using the Am29000TM Streamlined Instruction Proces-
sor
The extremely high instruction rate achieved by this proces-
sor places extraordinary demands on memory system de-
signs if maximum throughput is to be sustained and costs
minimized
The most obvious solution to the problem of access speed
is to implement system memory using high-speed static
memories However the high cost and low density of these
devices make them an expensive and space consumptive
solution
A more cost effective method of solving this problem is via
the use of dynamic RAMs Their high density and low cost
make their use extremely attractive The impediment to their
use is their relatively slow access times
However when operated in page mode dynamic RAMs be-
have more like static memories Properly managed they
can yield access times approaching those of fully static
RAMs
Block Diagram
Typical System Configuration
The function of NSBMC290 is to interface the page mode
access protocol of dynamic RAMs with the more general
burst mode access protocol supported by the Am29000 lo-
cal channel The device manages a double banked arrang-
ment of dynamic RAMs such that when burst accesses are
permitted data can be read or written at the rate of one
word per system clock cycle
Packaged as a 124 pin PGA or 132 pin PQFP the
NSBMC290 drives memory arrays directly thus minimizing
design complexity and package count
Features
Y Interfaces directly to Am29000 Local Channel
Y Manages Page Mode Dynamic Memory devices
Y Supports DRAMs from 64 KB to 16 MB
Y Manages Instruction and or Data Memory
Y Very Low Power Consumption
Y On-Chip Memory Address Multiplexer Drivers
Y Flexible Instruction Data Bus Buffer Management
Y Software-Configured operational parameters
Y Auto-Configured Bank Size and Location
Y High-Speed CMOS Technology
Logic Symbol
TL V 11803 – 2
TL V 11803 – 1
This document contains information concerning a product that has been developed by National Semiconductor Corporation V3 Corporation This information
is intended to help in evaluating this product National Semiconductor Corporation V3 Corporation reserves the right to change and improve the specifications
of this product without notice
TRI-STATE is a registered trademark National Semiconductor Corporation
NSBMC290TM is a trademark of National Semiconductor Corporation
V29BMCTM is a trademark of V3 Corporation
Am29000TM is a trademark of Advanced Micro Devices Sunnyvale California USA
C1995 National Semiconductor Corporation TL V 11803
RRD-B30M115 Printed in U S A
1 page  
Pin Descriptions (Continued)
MEMORY INTERFACE
The NSBMC290 is designed to drive a memory array orga-
nized as 2 banks each of 32 bits The address and control
signals for the memory array are output through high current
drivers in order to minimize the propagation delay due to
memory input impedance and trace capacitance External
array drivers are not required The address and control sig-
nals however must be externally terminated
Pin
A(A B)0 – 10
RAS(A B)
CAS(A B)0-3
MWE(A B)
Description
Multiplexed Addresses (Output High Current) These two buses transfer the multiplexed row and column
addresses to the memory array banks A and B respectively
Row Address Strobes (Output High Current Active Low) These signals are strobes that indicate the
existence of a valid row address on A(A B)0 – 10 These signals are to be connected to the two interleaved banks
of memory One is assigned to each bank
Column Address Strobe (Output High Current Active Low) These signals are strobes that indicate a valid
column address on A(A B)0–10 A set of each of these (A B) are assigned to each memory bank and within each
set one is assigned to each byte of the 32-bit memory
Memory Write Enable (Output High Current Active Low) These signals are the write strobes for the DRAM
memories One is supplied for each of the two banks of memory although they are logically identical
BUFFER CONTROLS
In order not to limit system implementation strategies vis j
vis instruction and data bus organization the NSBMC290
permits the designer to keep these busses separate or not
as performance criteria dictate In order to maintain bus
separation data buffers are required In order to maximize
performance these buffers are controlled directly by the
NSBMC290
Pin
DBLE(A B)
DBTX(A B)
IBTX(A B)
Description
Data Bus Latch Enable A and B (Output Active High) These outputs are used to enable transparent latches to
latch data from the Processor data bus to each bank of memory during a write cycle (Data access only)
The following buffer control outputs are multi-mode signals The signal names as they appear on the logic symbol
are the default signal names (Mode e 0) A more complete description is presented in the configuration section
Data Bus Transmit A and B (Output Active Low) These outputs are used during read cycles to enable data
from the individual banks of memory to drive the data bus
Instruction Bus Transmit A and B (Output Active Low) These outputs are used during instruction cycles to
enable data from the individual banks of memory to drive the instruction bus
5
5 Page 
CPU INTERFACE
The NSBMC290 interface to the Am29000 has been de-
signed for direct interconnect Normally it is not necessary
to place other logic devices between the processor
NSBMC290 and memory with the exception of Instruction
Data bus buffers The introduction of intermediate buffers
can result in skews or delays that will require that the sys-
tem clock frequency be derated for operation under worst
case conditions
SIMPLE ACCESS SEQUENCE
The NSBMC290 can return data to the processor in only 4
clocks or 5 clocks for a simple access depending on the
mode chosen (Configuration Bit 17) If multiple access
cycles are requested back to back then the BMC will pause
for a minimum of 2 clocks between RAS cycles to insure
that the RAS precharge time is met resulting in 5 clocks or 6
clocks between successive simple cycles (depending on
Configuration bit 17)
All access modes begin their cycle in the same fashion as a
simple access A simple access can become either a pipe-
lined or burst access if the appropriate inputs are driven
Figure 3 shows the timing relationship between the system
clock processor control signals and NSBMC290 outputs
All NSBMC290 outputs are derived synchronously with the
exception of tARA7 (processor address to memory address
delay) The shaded section in Figure 3 represents the extra
cycle inserted when the configuration register is initialized
with bit 17 cleared
DBTX DBTXa DBTXb DBCE DBCEa DBCEb IBTX IBTXa IBTXb
FIGURE 3 Simple Access Sequence
TL V 11803 – 6
11
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