NS32FX100-15 Datasheet PDF - National
| Part Number | NS32FX100-15 | |
| Description | System Controller | |
| Manufacturers | National | |
| Logo |  |
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There is a preview and NS32FX100-15 download ( pdf file ) link at the bottom of this page. Total 30 Pages | ||
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PRELIMINARY
July 1992
NS32FX100-15 NS32FX100-20 NS32FV100-20
NS32FV100-25 NS32FX200-20 NS32FX200-25
System Controller
General Description
The NS32FX200 NS32FV100 and NS32FX100 are highly
integrated system chips designed for a FAX system based
on National Semiconductor’s embedded processors
NS32FX161 NS32FV16 or NS32FX164 The NS32FX100 is
the common core for all three system chips The
NS32FV100 and NS32FX200 offer additional functions
Throughout this document references to the NS32FX100
also apply to both the NS32FV100 and the NS32FX200
Specific NS32FV100 or NS32FX200 features are explicitly
indicated
The NS32FX200 NS32FV100 and NS32FX100 feature an
interface to devices like stepper motors printers and scan-
ners a Sigma-Delta CODEC an elapsed-time counter a
DMA controller an interrupt controller and a UART
The NS32FX200 is optimized for high-end FAX applications
such as plain-paper FAX and multifunctional peripherals
The NS32FX100 is optimized for low-cost FAX applica-
tions The NS32FV100 is optimized for thermal paper FAX
machines with Digital Answering Machine support
Features
Y Direct interface to the NS32FX161 NS32FV16 and
NS32FX164 embedded processors
Y Supports a variety of Contact Image Sensor (CIS) and
Charge Coupled Device (CCD) scanners
Y Direct interface to a variety of Thermal Print Head
(TPH) printers Bitmap shifter and DMA channels facili-
tate the connection of other types of printers
Y Supports two stepper motors
Y Direct interface to ROM and SRAM The NS32FX200
and NS32FV100 in addition interface to DRAM
devices
Y Programmable wait state generator
Y Demultiplexed address and data buses
Y Multiplexed DRAM address bus (NS32FX200 and
NS32FV100)
Y Supports 3V freeze mode by maintaining only elapsed
time counter
Y Control of power consumption by disabling inactive
modules and reducing the clock frequency
Y Operating frequency
Normal mode 19 6608 MHz 24 576 MHz in steps
of 1 2288 MHz (NS32FX200)
Normal mode 19 6608 MHz 24 576 MHz in steps
of 1 2288 MHz (NS32FV100)
Normal mode 14 7456 MHz 19 6608 MHz in steps
of 1 2288 MHz (NS32FX100)
Power Save mode Normal mode frequency divided
by sixteen
Y On-Chip full duplex Sigma-Delta CODEC with
Total harmonic distortion better than b70 dB
Programmable hybrid balance filter
Programmable reception and transmission filters
Programmable gain control
Y On-Chip Interrupt Control Unit with
16 interrupt sources
Programmable triggering mode
Y On-Chip counters WATCHDOGTM UART
MICROWIRETM System Clock Generator and I O
ports
Y On-Chip DMA controller (NS32FX200 four channels
NS32FX100 NS32FV100 three channels)
Y Up to 37 on-chip general purpose I O pins expandable
externally
Y Flexible allocation of I O and modules’ pins
Y 132-pin JEDEC PQFP package
FIGURE 1-1 A FAX Controller Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
MICROWIRETM and WATCHDOGTM are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL EE11331
TL EE 11331 – 1
RRD-B30M105 Printed in U S A
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List of Figures (Continued)
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FIGURE 4-21
FIGURE 4-22
FIGURE 4-23
FIGURE 4-24
FIGURE 4-25
FIGURE 4-26
FIGURE 4-27
Connection Diagram Top View
Analog Circuitry Block Diagram
TTL Output Signals Specification Standard
TTL Input Signals Specification Standard
CMOS Output Signals Specification Standard
CMOS Input Signals Specification Standard
Input Hysteresis
Clock Waveforms
DRAM Read Bus Cycle
DRAM Write Bus Cycle
ROM SRAM Read Bus Cycle
ROM SRAM Write Bus Cycle (One Wait State)
I O Read Bus Cycle
I O Write Bus Cycle
DRAM Refresh Bus Cycles
DMA Read Transaction (DIR e 0)
DMA Write Transaction (DIR e 1)
Interrupt Signals Timing
Sigma-Delta Signals Timing
SBYPS Input Signal Timing
Printer Signals Timing
Reset Signals Timing
Scanner Signals Timing
UART Signals Timing
MWIRE Signals Timing
Ports Signals Timing
Analog Signals Timing
List of Tables
TABLE 2-1
TABLE 2-2
TABLE 2-3
TABLE 2-4
TABLE 2-5
TABLE 3-1
TABLE 3-2
TABLE A-1
TABLE A-2
CTTL MCLON and MCLOFF Values
Component Values
Interrupt Sources and Priority Levels
DRAM Address Multiplexing
DRAM Address Sizes
R C and L Values
System Chip Operation Modes and Power Consumption
Transmitter Performance
Receiver Performance
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for NS32FX100-15 electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ NS32FX100-15.PDF Datasheet ] | |
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