DataSheetWiki


NM34C02 fiches techniques PDF

Fairchild - 2K-Bit Standard 2-Wire Bus Interface

Numéro de référence NM34C02
Description 2K-Bit Standard 2-Wire Bus Interface
Fabricant Fairchild 
Logo Fairchild 





1 Page

No Preview Available !





NM34C02 fiche technique
March 1999
NM34C02
2K-Bit Standard 2-Wire Bus Interface
Designed with Permanent Write-Protection for First 128 Bytes for Serial Presence
Detect Application on Memory Modules
General Description
Features
The NM34C02 is 2048 bits of CMOS non-volatile electrically
erasable memory. It is designed to support Serial Presence
Detect circuitry in memory modules. This communications proto-
col uses CLOCK (SCL) and DATA I/O (SDA) lines to synchro-
nously clock data between the master (for example a micropro-
cessor) and the slave EEPROM device(s).
The contents of the non-volatile memory allows the CPU to
determine the capacity of the module and the electrical character-
istics of the memory devices it contains. This will enable "plug and
play" capability as the module is read and PC main memory
resources utilized through the memory controller.
The first 128 bytes of the memory of the NM34C02 can be
permanently Write Protected by writing to the "WRITE PROTECT"
Register. Write Protect implementation details are described
under the section titled Addressing the WP Register.
The NM34C02 is available in a JEDEC standard TSSOP package
for low profile memory modules for systems requiring efficient
space utilization such as in a notebook computer. Two options are
available: L - Low Voltage and LZ - Low Power, allowing the part
to be used in systems where battery life is of primary importance.
s Extended Operating Voltage: 2.7V-5.5V
s Write-Protection for first 128 bytes
s 200 µA active current typical
– 10 µA standby current typical
– 1.0 µA standby current typical (L)
– 0.1 µA standby current typical (LZ)
s IIC compatible interface
– Provides bidirectional data transfer protocol
s Sixteen byte page write mode
– Minimizes total write time per byte
s Self timed write cycle
- Typical write cycle time of 6ms
s Endurance: 1,000,000 data changes
s Data retention greater than 40 years
s Packages available: 8-pin TSSOP and 8-pin SO
Block Diagram
VCC
VSS
SDA
SCL
A2
A1
A0
START
STOP
LOGIC
START CYCLE
H.V. GENERATION
TIMING &CONTROL
SLAVE ADDRESS
REGISTER &
COMPARATOR
CONTROL
LOGIC
LOAD
INC
XDEC
16
E2PROM
ARRAY
16 x 16 x 8
WORD
ADDRESS
COUNTER
R/W
0/1/2/3
4
4
16
YDEC
Write Protect
Register
Device Address Bits
DIN
8
CK
DATA REGISTER
DOUT
DS012821-1
© 1999 Fairchild Semiconductor Corporation
NM34C02 Rev. D.2
1
www.fairchildsemi.com

PagesPages 12
Télécharger [ NM34C02 ]


Fiche technique recommandé

No Description détaillée Fabricant
NM34C02 2K-Bit Standard 2-Wire Bus Interface Fairchild
Fairchild

US18650VTC5A

Lithium-Ion Battery

Sony
Sony
TSPC106

PCI Bus Bridge Memory Controller

ATMEL
ATMEL
TP9380

NPN SILICON RF POWER TRANSISTOR

Advanced Semiconductor
Advanced Semiconductor


www.DataSheetWiki.com    |   2020   |   Contactez-nous  |   Recherche