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PDF 8XL196NP Data sheet ( Hoja de datos )
| Número de pieza | 8XL196NP | |
| Descripción | COMMERCIAL CHMOS 16-BIT MICROCONTROLLER | |
| Fabricantes | Intel Corporation | |
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8XL196NP COMMERCIAL
CHMOS 16-BIT MICROCONTROLLER
n 14 MHz Operation at 2.7–3.3 Volts
n 1 Mbyte of Linear Address Space
n Optional 4 Kbytes of ROM
n 1000 Bytes of Register RAM
n Register-register Architecture
n 32 I/O Port Pins
n 16 Prioritized Interrupt Sources
n 4 External Interrupt Pins and NMI Pin
n 2 Flexible 16-bit Timer/Counters with
Quadrature Counting Capability
n 3 Pulse-width Modulator (PWM) Outputs
with High Drive Capability
n Full-duplex Serial Port with Dedicated
Baud-rate Generator
n Peripheral Transaction Server
n Event Processor Array (EPA) with 4 High-
speed Capture/Compare Channels
n Chip-select Unit
— 6 Chip Select Pins
— Dynamic Demultiplexed/Multi-
plexed Address/Data Bus for Each
Chip Select
— Programmable Wait States (0, 1, 2,
or 3) for Each Chip Select
— Programmable Bus Width (8- or 16-
bit) for Each Chip Select
— Programmable Address Range for
Each Chip Select
n 2.0µs 16 × 16 Unsigned Multiplication
n 3.4µs 32/16 Unsigned Division
n 100-pin SQFP or 100-pin QFP Package
n Complete System Development
Support
n High-speed CHMOS Technology
The 8XL196NP is a member of Intel’s 16-bit MCS® 96 microcontroller family. The device features 1 Mbyte of
linear address space, a demultiplexed bus, and a chip-select unit. The external bus can dynamically switch
between multiplexed and demultiplexed operation. When operating at 14 MHz in demultiplexed mode, the
8XL196NP can access a 200 ns memory device with zero wait states. The 8XL196NP is available without
ROM (80L196NP) or with 4 Kbytes of ROM (83L196NP).
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringe-
ment of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such
products. Information contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 1996
March 1996
Order Number: 272824-001
1 page  
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 2. 8XL196NP 100-pin SQFP Pin Assignment
Pin Name Pin Name Pin Name Pin Name
1 RESET#
2 NMI
26 EXTINT3/P3.7
27 EPA0/P1.0
51 CLKOUT/P2.7
52 NC†
76 WR#/WRL#
77 EPORT.3/A19
3 EA#
4 A0
5 A1
6 VCC
7 VSS
8 A2
28 VCC
29 EPA1/P1.1
30 EPA2/P1.2
31 EPA3/P1.3
32 T1CLK/P1.4
33 T1DIR/P1.5
53 VSS
54 XTAL2
55 XTAL1
56 VSS
57 NC†
58 A15
78 EPORT.2/A18
79 VSS
80 VCC
81 EPORT.1/A17
82 EPORT.0/A16
83 AD15
9 A3
10 A4
34 VCC
35 T2CLK/P1.6
59 A14
60 A13
84 AD14
85 AD13
11 A5
12 A6
36 VSS
37 T2DIR/P1.7
61 A12
62 A11
86 AD12
87 AD11
13 A7
38 PWM0/P4.0
63 A10
88 AD10
14 VCC
15 VSS
16 NC†
17 NC†
18 CS0#/P3.0
19 CS1#/P3.1
39 PWM1/P4.1
40 PWM2/P4.2
41 P4.3
42 VCC
43 VSS
44 TXD/P2.0
64 A9
65 A8
66 VSS
67 VCC
68 VSS
69 ONCE
89 AD9
90 VSS
91 AD8
92 VCC
93 AD7
94 AD6
20 CS2#/P3.2
45 RXD/P2.1
70 RPD
95 AD5
21 CS3#/P3.3
46 EXTINT0/P2.2
71 READY
96 AD4
22 VSS
23 CS4#/P3.4
47 BREQ#/P2.3
48 EXTINT1/P2.4
72 INST
73 ALE
97 AD3
98 AD2
24 CS5#/P3.5
49 HOLD#/P2.5
74 BHE#/WRH#
99 AD1
25 EXTINT2/P3.6
50 HLDA#/P2.6
75 RD#
100 AD0
† To be compatible with future versions of the Nx family, tie the no connection (NC) pins as follows:
Pin 57 = VSS, Pin 16 = VCC, Pin 17 = VSS (5 volts on this pin will enable a clock doubler on future
devices), and Pin 52 = VCC.
5
5 Page 
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Name
BHE#
BREQ#
CLKOUT
CS5#:0
Table 6. Signal Descriptions (Continued)
Type
O
Description
Byte High Enable†
During 16-bit bus cycles, this active-low output signal is asserted for word and high-
byte reads and writes to external memory. BHE# indicates that valid data is being
transferred over the upper half of the system data bus. Use BHE#, in conjunction
with address bit 0 (A0 for a demultiplexed address bus, AD0 for a multiplexed
address/data bus), to determine which memory byte is being transferred over the
system bus:
BHE# AD0 or A0 Byte(s) Accessed
00
01
10
both bytes
high byte only
low byte only
BHE# shares a package pin with WRH#.
† When this pin is configured as a special-function signal (P5_MODE.5 = 1), the
chip configuration register 0 (CCR0) determines whether it functions as BHE# or
WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#.
O Bus Request
This active-low output signal is asserted during a hold cycle when the bus controller
has a pending external memory cycle. When the bus-hold protocol is enabled
(WSR.7 is set), the P2.3/BREQ# pin can function only as BREQ#, regardless of the
configuration selected through the port configuration registers (P2_MODE,
P2_DIR, and P2_REG). An attempt to change the pin configuration is ignored until
the bus-hold protocol is disabled (WSR.7 is cleared).
The microcontroller can assert BREQ# at the same time as or after it asserts
HLDA#. Once it is asserted, BREQ# remains asserted until HOLD# is deasserted.
BREQ# shares a package pin with P2.4.
O Clock Output
Output of the internal clock generator. The CLKOUT frequency is ½ the internal
operating frequency (f). CLKOUT has a 50% duty cycle.
CLKOUT shares a package pin with P2.7.
O Chip-select Lines 0–5
The active-low output CSx# is asserted during an external memory cycle when the
address to be accessed is in the range programmed for chip select x. If the external
memory address is outside the range assigned to the six chip selects, no chip-
select output is asserted and the bus configuration defaults to the CS5# values.
Immediately following reset, CS0# is automatically assigned to the range FF2000–
FF20FFH (F2000–F20FFH if external).
CS5:0# share package pins with P3.5:0.
11
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