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PDF 8XC51 Data sheet ( Hoja de datos )
| Número de pieza | 8XC51 | |
| Descripción | CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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8XC51GB
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Commercial Express
87C51GB 8 Kbytes OTP 8 Kbytes Internal Program Memory
83C51GB 8 Kbytes Factory Programmable ROM
80C51GB CPU with RAM and I O
8XC51GB 3 5 MHz to 12 MHz g20% VCC
8XC51GB-1 3 5 MHz to 16 MHz g20% VCC
Y 8 Kbytes On-Chip ROM OTP ROM
Y 256 Bytes of On-Chip Data RAM
Y Two Programmable Counter Arrays
with
2 x 5 High Speed Input Output
Channels Compare Capture
Pulse Width Modulators
Watchdog Timer Capabilities
Y Three 16-Bit Timer Counters with
Four Programmable Modes
Capture Baud Rate Generation
(Timer 2)
Y Dedicated Watchdog Timer
Y 8-Bit 8-Channel A D with
Eight 8-Bit Result Registers
Four Programmable Modes
Y Programmable Serial Channel with
Framing Error Detection
Automatic Address Recognition
Y Serial Expansion Port
Y Programmable Clock Out
Y Extended Temperature Range
(b40 C to a85 C)
Y 48 Programmable I O Lines with
40 Schmitt Trigger Inputs
Y 15 Interrupt Sources with
7 External 8 Internal Sources
4 Programmable Priority Levels
Y Pre-Determined Port States on Reset
Y High Performance CHMOS Process
Y TTL and CHMOS Compatible Logic
Levels
Y Power Saving Modes
Y 64K External Data Memory Space
Y 64K External Program Memory Space
Y Three Level Program Lock System
Y ONCE (ON-Circuit Emulation) Mode
Y Quick Pulse Programming Algorithm
Y MCS 51 Microcontroller Fully
Compatible Instruction Set
Y Boolean Processor
Y Oscillator Fail Detect
Y Available in 68-Pin PLCC
MEMORY ORGANIZATION
PROGRAM MEMORY Up to 8 Kbytes of the program memory can reside in the on-chip ROM Also the device
can address up to 64K of program memory external to the chip
DATA MEMORY This microcontroller has a 256 x 8 on-chip RAM In addition it can address up to 64 Kbytes of
external data memory
The Intel 8XC51GB is a single-chip control oriented microcontroller which is fabricated on Intel’s CHMOS III-E
technology The 8XC51GB is an enhanced version of the 8XC51FA and uses the same powerful instruction
set and architecture as existing MCS 51 microcontroller products Added features make it an even more
powerful microcontroller for applications that require On-Chip A D Pulse Width Modulation High Speed I O
up down counting capabilities and memory protection features It also has a more versatile serial channel that
facilitates multi-processor communications
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
November 1994
Order Number 272337-002
1 page  
8XC51GB
This pin also receives the 12 75V programming sup-
ply voltage (VPP) during programming (OTP only)
XTAL1 Input to the inverting oscillator amplifier
XTAL2 Output from the inverting oscillator amplifi-
er
A D CONVERTER
The 8XC51GB A D converter has a resolution of 8
bits and an accuracy of g1 LSB (g2 LSB for chan-
nels 0 and 1) The conversion time for a single chan-
nel is 20 ms at a clock frequency of 16 MHz with the
sample and hold function included Independent
supply voltages are provided for the A D Also the
A D operates both in Normal Mode or in Idle Mode
The A D has 8 analog input pins ACH0 (A D CHan-
nel 0) ACH7 1 reference input pin COMPREF
(COMParison REFerence) 1 control input pin TRI-
GIN (TRIGger IN) and 2 power pins AVREF (Volt-
age REFerence) and analog ground (ANalog
GrouND) In addition the A D has 8 conversion re-
sult registers ADRES0 (A D result for channel 0)
ADRES7 1 comparison result register ACMP (Ana-
log Comparison) and 1 control register ACON (A D
Control)
The control bit ACE (A D Conversion Enable) in
ACON controls whether the A D is in operation or
not ACE e 0 idles the A D ACE e 1 enables A D
conversion The control bit AIM (A D Input mode) in
ACON controls the mode of channel selection AIM
e 0 is the Scan Mode and AIM e 1 is the Select
Mode The result registers ADRES4 ADRES7 al-
ways contain the result of a conversion from the cor-
responding channels ACH4 CH7 However the
result registers ADRES0 ADRES3 depend on the
mode selected In the scan mode ADRES0 AD-
RES3 contain the values from ACH0 ACH3 In
the Select Mode one of the four channels ACH0
ACH3 is converted four times and the four values
are stored sequentially in locations ADRES0 AD-
RES3 Its channel is selected by bits ACS1 and
ACS0 (A D Channel Select 1 and 0) in ACON
PROGRAMMABLE COUNTER ARRAYS
The Programmable Counter Arrays (PCA–PCA1) are
each made up of a Counter Module and five Regis-
ter Comparator Modules as shown below The
16-bit output of the counter module is available to all
five Register Comparator Modules providing one
common timing reference Each Register Compara-
tor Module is associated with a pin of Port 1 or Port 4
and is capable of performing input capture output
compare and pulse width modulation functions The
PCAs are exactly the same in function except for the
addition of clock input sources on PCA1
The PCA Counter and five Register Comparator
Modules each have a status bit in the CCON
C1CON Special Function Registers These six
status bits are set according to the selected modes
of operation described below The CCON C1CON
Register provides a convenient means to determine
which of the six PCA PCA1 interrupts has occurred
The EC Bit in the IE (Interrupt Enable) Special Func-
tion Register is a global interrupt enable for the PCA
272337 – 3
Figure 3 Programmable Counter Arrays
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output respec-
tively of an inverting amplifier which can be config-
ured for use as an on-chip oscillator as shown in
Figure 4 Either a quartz crystal or ceramic resonator
may be used More detailed information concerning
the use of the on-chip oscillator is available in Appli-
cation Note AP-155 ‘‘Oscillators for Microcontrol-
lers ’’ Order No 230659
To drive the device from an external clock source
XTAL should be driven while XTAL2 floats as
shown in Figure 5 There are no requirements on the
duty cycle of the external clock signal since the in-
put to the internal clocking circuitry is through a di-
vide-by-two flip-flop but minimum and maximum
high and low times specified on the data sheet must
be observed
5
5 Page 
8XC51GB
EXPLANATION OF THE AC SYMBOLS
L Logic Level LOW or ALE
Each timing symbol has 5 characters The first char-
acter is always a ‘‘T’’ (stands for time) The other
characters depending on their positions stand for
P PSEN
Q Output Data
R RD Signal
the name of a signal or the logical status of that
signal The following is a list of all the characters and
what they stand for
A Address
C Clock
D Input Data
H Logic Level HIGH
I Instruction (Program Memory Contents)
AC SPECIFICATIONS
T Time
V Valid
W WR Signal
X No Longer a Valid Logic Level
Z Float
For Example
TAVLL e Time from Address Valid to ALE Low
TLLPL e Time from ALE Low to PSEN Low
Over Operating Conditions Load Capacitance on Port 0 ALE and PSEN e 100 pF Load Capacitance on all
other outputs e 80 pF
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
Symbol
Parameter
12 MHz Osc
Min Max
Variable Osc
Min Max
Units
1 TCLCL Osc Freq
TLHLL ALE Pulse Width
3 5 16 MHz
127 2TCLCL b 40
ns
TAVLL ADDR Valid to ALE Low
43
TCLCL b 40
ns
TLLAX ADDR Hold after ALE Low
53
TCLCL b 30
ns
TLLIV
ALE Low to Valid Inst IN
234
4TCLCL b 100 ns
TLLPL ALE LOW to PSEN LOW
53
TCLCL b 30
ns
TPLPH PSEN Pulse Width 205 3TCLCL b 45
ns
TPLIV
PSEN Low to Valid Instr In
145
3TCLCL b 105 ns
TPXIX
Input Instr Hold after PSEN
0
0
ns
TPXIZ
Input Instr Float after PSEN
59
TCLCL b 25 ns
TAVIV ADDR to Valid Instr In
312
5TCLCL b 105 ns
TPLAZ PSEN Low to ADDR Float
10
10 ns
TRLRH RD Pulse Width
400 6TCLCL b 100
ns
TWLWH WR Pulse Width
400 6TCLCL b 100
ns
TRLDV RD Low to Valid Data In
252
5TCLCL b 165 ns
TRHDX Data Hold after RD
0
0
ns
TRHDZ Data Float after RD
107 2TCLCL b 60 ns
TLLDV ALE Low to Valid Data In
517
8TCLCL b 150 ns
TAVDV ADDR to Valid Data In
585
9TCLCL b 165 ns
TLLWL ALE Low to RD or WR Low
200 300 3TCLCL b 50 3TCLCL a 50 ns
TAVWL ADDR Valid to RD or WR Low 203
4TCLCL b 130
ns
TQVWX Data Valid to WR Transition
33
TCLCL b 50
ns
TWHQX Data Hold after WR
TQVWH Data Valid to WR High
33
433
TCLCL b 50
7 TCLCL b 150
ns
ns
TRLAZ RD Low to Addr Float
0
0 ns
TWHLH RD or WR High to ALE High 43 123 TCLCL b 40 TCLCL a 40 ns
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet 8XC51.PDF ] | |
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