87C751 Datasheet PDF - NXP Semiconductors
| Part Number | 87C751 | |
| Description | 80C51 8-bit microcontroller family 2K/64 OTP/ROM/ I2C/ low pin count | |
| Manufacturers | NXP Semiconductors | |
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INTEGRATED CIRCUITS
83C751/87C751
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
Product specification
Supersedes data of 1998 Jan 19
IC20 Data Handbook
1998 May 01
Philips
Semiconductors
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Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
Product specification
83C751/87C751
PIN DESCRIPTIONS
MNEMONIC
VSS
VCC
P0.0–P0.2
P1.0–P1.7
P3.0–P3.7
RST
X1
PIN NO.
DIP/
SSOP
LCC
TYPE
NAME AND FUNCTION
12 14
I Circuit Ground Potential
24 28
I Supply voltage during normal, idle, and power-down operation.
8–6 9–7 I/O Port 0: Port 0 is a 3-bit open-drain, bidirectional port. Port 0 pins that have 1s written to them float,
and in that state can be used as high-impedance inputs. Port 0 also serves as the serial I2C
interface. When this feature is activated by software, SCL and SDA are driven low in accordance
with the I2C protocol. These pins are driven low if the port register bit is written with a 0 or if the I2C
subsystem presents a 0. The state of the pin can always be read from the port register by the
program.
To comply with the I2C specification, P0.0 and P0.1 are open drain bidirectional I/O pins with the
electrical characteristics listed in the tables that follow. While these differ from “standard TTL”
characteristics, they are close enough for the pins to still be used as general-purpose I/O in
non-I2C applications. Port 0 also provides alternate functions for programming the EPROM
memory as follows:
6 7 N/A VPP (P0.2) – Programming voltage input. (See Note 1.)
7 8 I OE/PGM (P0.1) – Input which specifies verify mode (output enable) or the program mode.
OE/PGM = 1 output enabled (verify mode).
OE/PGM = 0 program mode.
8 9 I ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3.
ASEL = 0 low address byte available on port 3.
ASEL = 1 high address byte available on port 3 (only the three least significant bits are used).
7 8 I/O SDA (P0.1) – I2C data.
8 9 I/O SCL (P0.0) – I2C clock.
13–20 15–20, I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written
23, 24
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins
that are externally pulled low will source current because of the internal pull-ups. (See DC
Electrical Characteristics: IIL). Port 1 serves to output the addressed EPROM contents in the verify
mode and accepts as inputs the value to program into the selected address during the program
mode. Port 1 also serves the special function features of the 80C51 family as listed below:
18 20
I INT0 (P1.5): External interrupt.
19 23
I INT1 (P1.6): External interrupt.
20 24
I T0 (P1.7): Timer 0 external input.
5–1, 6, 4–1, I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written
23–21 27–25
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins
that are externally being pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: IIL). Port 3 also functions as the address input for the EPROM memory location to
be programmed (or verified). The 11-bit address is multiplexed into this port as specified by
P0.0/ASEL.
9 11 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device.
An internal diffused resistor to VSS permits a power-on RESET using only an external capacitor to
VCC. After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places
the device in the programming state allowing programming address, data and VPP to be applied for
programming or verification purposes. The RESET serial sequence must be synchronized with the
X1 input.
11 13 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
X1 also serves as the clock to strobe in a serial bit stream into RESET to place the device in the
programming state.
X2 10 12 O Crystal 2: Output from the inverting oscillator amplifier.
NOTE:
1. When P0.2 is at or close to 0V it may affect the internal ROM operation. We recommend that P0.2 be tied to VCC via a small pullup
(e.g., 2kΩ).
1998 May 01
5
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| Information | Total 24 Pages | |
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