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PDF MXD1210ESA Data sheet ( Hoja de datos )
| Número de pieza | MXD1210ESA | |
| Descripción | Nonvolatile RAM Controller | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-0154; Rev 2; 11/05
Nonvolatile RAM Controller
General Description
The MXD1210 nonvolatile RAM controller is a very low-
power CMOS circuit that converts standard (volatile)
CMOS RAM into nonvolatile memory. It also continually
monitors the power supply to provide RAM write protec-
tion when power to the RAM is in a marginal (out-of-tol-
erance) condition. When the power supply begins to
fail, the RAM is write-protected, and the device switch-
es to battery-backup mode.
Microprocessor Systems
Computers
Embedded Systems
Applications
Pin Configurations
TOP VIEW
VCCO 1
VBATT1 2
TOL 3
GND 4
MXD1210
8 VCCI
7 VBATT2
6 CEO
5 CE
DIP/SO
Features
♦ Battery Backup
♦ Memory Write Protection
♦ 230µA Operating Mode Quiescent Current
♦ 2nA Backup Mode Quiescent Current
♦ Battery Freshness Seal
♦ Optional Redundant Battery
♦ Low Forward-Voltage Drop on VCC Supply Switch
♦ 5% or 10% Power-Fail Detection Options
♦ Tests Battery Condition During Power-Up
♦ 8-Pin SO Available
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MXD1210C/D
0°C to +70°C
Dice*
MXD1210CPA
0°C to +70°C
8 PDIP
MXD1210CSA
0°C to +70°C
8 SO
MXD1210CWE
0°C to +70°C
16 Wide SO
MXD1210EPA
-40°C to +85°C
8 PDIP
MXD1210ESA
-40°C to +85°C
8 SO
MXD1210EWE
-40°C to +85°C
16 Wide SO
MXD1210MJA
-55°C to +125°C
8 CERDIP
*Contact factory for dice specifications.
Devices in PDIP and SO packages are available in both lead-
ed and lead-free packaging. Specify lead free by adding the +
symbol at the end of the part number when ordering. Lead free
not available for CERDIP package.
Typical Operating Circuit
N.C. 1
VCCO 2
N.C. 3
VBATT1 4
N.C. 5
TOL 6
N.C. 7
GND 8
MXD1210
16 N.C.
15 VCCI
14 N.C.
13 VBATT2
12 N.C.
11 CEO
10 N.C.
9 CE
WIDE SO
+5V VCCI 8
1
2
MXD1210 7
CE 5
FROM
DECODER
4
6
3
VCCO
VBATT1
VBATT2
VCC
CMOS
RAM
CE
GND
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Nonvolatile RAM Controller
Detailed Description
Main Functions
The MXD1210 executes five main functions to perform
reliable RAM operation and battery backup (see the
Typical Operating Circuit and Figure 1):
1) RAM Power-Supply Switch: The switch directs
power to the RAM from the incoming supply or
from the selected battery, whichever is at the
greater voltage. The switch control uses the same
criterion to direct power to MXD1210 internal cir-
cuitry.
2) Power-Failure Detection: The write-protection
function is enabled when a power failure is
detected. The power-failure detection range
depends on the state of the TOL pin as follows:
CONDITION
TOL = GND
TOL = VCCO
VCCTP RANGE (V)
4.75 to 4.50
4.50 to 4.25
Power-failure detection is independent of the bat-
tery-backup function and precedes it sequentially
as the power-supply voltage drops during a typi-
cal power failure.
3) Write Protection: This holds the chip-enable out-
put (CEO) to within 0.2V of VCCI or of the selected
battery, whichever is greater. If the chip-enable
input (CE) is low (active) when power failure is
detected, then CEO is held low until CE is brought
high, at which time CEO is gated high for the
duration of the power failure. The preceding
sequence completes the current RD/WR cycle,
preventing data corruption if the RAM access is a
WR cycle.
4) Battery Redundancy: A second battery is option-
al. When two batteries are connected, the
stronger battery is selected to provide RAM back-
up and to power the MXD1210. The battery-selec-
tion circuitry remains active while in the
battery-backup mode, selecting the stronger bat-
tery and isolating the weaker one. The battery-
selection activity is transparent to the user and
the system. If only one battery is connected, the
second battery input should be grounded.
5) Battery-Status Warning: This notifies the system
when the stronger of the two batteries measures ≤
2.0V. Each time the MXD1210 is repowered (VCCI
> VCCTP) after detecting a power failure, the bat-
tery voltage is measured. If the battery in use is
low, following the MXD1210 recovery period, the
device issues a warning to the system by inhibit-
ing the second memory cycle. The sequence is
as follows:
First access: read memory location n, loc(n) = x
Second access: write memory location n,
loc(n) = complement (x)
Third access: read memory location n, loc(n) = ?
If the third access (read) is complement (x), then the
battery is good; otherwise the battery is not good.
Return to loc(n) = x following the test sequence.
Freshness-Seal Mode
The freshness-seal mode relates to battery longevity
during storage rather than directly to battery backup.
This mode is activated when the first battery is con-
nected, and is defeated when the voltage at VCCI first
exceeds VCCTP. In the freshness-seal mode, both bat-
teries are isolated from the system; that is, no current is
drained from either battery, and the RAM is not pow-
ered by either battery. This means that batteries can be
installed and the system can be held in inventory with-
out battery discharge. The positive edge rate at
VBATT1 and VBATT2 should exceed 0.1V/µs. The bat-
teries will maintain their full shelf life while installed in
the system.
Battery Backup
The Typical Operating Circuit shows the MXD1210 con-
nected to write-protect the RAM when VCC is less than
4.75V, and to provide battery backup to the supply.
_______________________________________________________________________________________ 5
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet MXD1210ESA.PDF ] | |
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