|
|
PDF MX98715AEC-D Data sheet ( Hoja de datos )
| Número de pieza | MX98715AEC-D | |
| Descripción | SINGLE CHIP FAST ETHERNET NIC CONTROLLER | |
| Fabricantes | Macronix International | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MX98715AEC-D (archivo pdf) en la parte inferior de esta página. Total 40 Páginas | ||
|
No Preview Available !
ADVANCED INFORMATION
MX98715AEC-D
SINGLE CHIP FAST ETHERNET NIC CONTROLLER
1. FEATURES
• A single chip solution integrates 100/10 Base-T fast
Ethernet MAC, PHY and PMD
• Microsoft PC97, 98, 99 and Novell 4.11/5.0 certified.
• Support DMI 2.0 management.
• Support Intel PXE remote boot device.
• Fully comply to IEEE 802.3u specification
• Operates over 100 meters of STP and cat 5 UTP cable
• Fully comply to PCI spec. 2.1 up to 33MHz
• Fully comply to Advanced Configuration and Power
Interface (ACPI) Rev 1.1
• Fully comply to PCI Bus Power Management Inter-
face spec. Rev 1.1
• Support full and half duplex operations in both 100
Base-TX and 10 Base-T mode
• Supports 3 kinds of wake up events defined in Net-
work Device Class Power Management Spec 1.0.
Including:
- Magic Packet
- Link Change (link-on)
- Wake Up Frames
• Supports IEEE802.3x Frame Based Flow Control
scheme in full duplex mode.
• Supports early interrupt on both transmit and receive
operations. • 100/10 Base-T NWAY auto-negotiation
function
• Large on-chip FIFOs for both transmit and receive
operations without external local memory
• Bus master architecture with linked host buffers deliv-
ers the most optimized performance
• 32-bit bus master DMA channel provides ultra low
CPU utilization suitable for server and windows appli-
cations.
• Proprietary Adaptive Network Throughput Control
(ANTC) technology to optimize data integrity and
throughput
• Support up to 64K bytes boot ROM interface
• Three levels of loopback diagnositic capability
• Support a variety of flexible address filtering modes
with 16 CAM addresses and 128 bits hash
• MicroWire interface to EEPROM for customer's IDs
and configuration data
• Single +5V power supply, CMOS technology, 128-pin
PQFP package.
( Magic packet technology is a trademark of advanced Micro De-
vice Corp. )
2. GENERAL DESCRIPTIONS
The MX98715AEC-D controller is an IEEE802.3u com-
pliant single chip 32-bit full duplex, 10/100Mbps highly
integrated Fast Ethernet combo solution, designed to
address high performance local area networking (LAN)
system application requirements.
MX98715AEC-D's PCI bus master architecture delivers
the optimized performance for future high speed and pow-
erful processor technologies. In other words, the
MX98715AEC-D not only keeps CPU utilization low while
maximizing data throughput, but it also optimizes the
PCI bandwidth providing the highest PCI bandwidth uti-
lization. To further reduce maintenance costs the
MX98715AEC-D uses drivers that are backward com-
patible with the original MXIC MX98715 series control-
lers.
The MX98715AEC-D contains a PCI local bus glueless
interface, a Direct Memory Access (DMA) buffer man-
agement unit, an IEEE802.3u-compliant Media Access
Controller (MAC), large Transmit and Receive FIFOs, and
an on-chip 10 Base-T and 100 Base-TX transceiver sim-
plifying system design and improving high speed signal
quality. Full-duplex operation are supported in both 10
Base-T and 100 Base-TX modes that increases the
controller's operating bandwidth up to 200Mbps.
Equipped with intelligent IEEE802.3u-compliant auto-
negotiation, the MX98715AEC-D-based adapter allows
a single RJ-45 connector to link with the other
IEEE802.3u-compliant device without re-configuration.
P/N:PM0719
REV. 0.1 ,FEB. 05, 2001
1
1 page  
MX98715AEC-D
Pin Name Type Pin No
PAR T/S 24
STOPB S/T/S 20
REQB
GNTB
T/S 115
I 114
BPA1
(EEDI)
O
61
BPA0
(EECK)
O
BPA[14:0] O
BPA15
/LED0
O
60
77-76,
73-70,
68-60
78
BPD0
T/S 58
(EEDO)
BPD[7:0] T/S
EECS
O
BOEB
O
RDA O
RTX O
RTX2EQ O
EQTEST2 I
RXIP
I
51-58
59
69
84
103
102
101
93
RXIN I 92
128 Pin Function and Driver
PCI bus parity bit: shared PCI bus even parity bit for 32 bits AD bus and CBE
bus.
PCI Target requested transfer stop signal: as bus master, assertion of STOPB
cause MX98715AEC-D either to retry, disconnect, or abort.
PCI bus request signal: to initiate a bus master cycle request
PCI bus grant acknowledge signal: host asserts to inform MX98715AEC-D
that access to the bus is granted
Boot PROM address bit 1(EECS=0): together with BPA[15:0] to access
external boot PROM up to 256KB.
EEPROM data in(EECS=1): EEPROM serial data input pin.
Boot PROM address bit 0(EECS=0): together with BPA[15:0] to access
external boot PROM up to 256KB.
EEPROM clock(EECS=1): EEPROM clock input pin
Boot PROM address line.
Boot PROM address line 15.
Programmable LED pin 0:
CSR9.28=1 Set the LED as Link Speed (10/100)LED.
CSR9.28=0 Set the LED as Activity LED.
Default is activity LED after reset.
<Note>:This pin acts as LED0 normally. It automatically switch to Boot
PROM address 15 function while accessing Boot PROM.
Boot PROM data line 0(EECS=0): boot PROM or flash data line 0.
EEPROM data out(EECS=1): EEPROM serial data outpin(during reset
initialization).
Boot PROM data lines: boot PROM or flash data lines 7-0.
EEPROM Chip Select pin.
Boot PROM Output Enable.
Connecting an external resistor to ground, Resistor value=510 ohms
Connecting an external resistor to ground, Resistor value=510 ohms
Connecting an external resistor to ground, Resistor value=1.5K ohms.
Not connected.
Twisted pair receive differential input: Support both 10 Base-T and 100
Base-TX receive differential input.
Twisted pair receive differential input: Support both 10 Base-T and 100
Base-TX receive differential input.
P/N:PM0719
REV. 0.1, FEB. 05, 2001
5
5 Page 
MX98715AEC-D
5.1.11 PCI DRIVER AREA REGISTER ( PFDA ) ( 43h-40h )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Board Type
Driver Special Use
bit 29 : board type
bit 15 - 8 : driver is free to read and write this field for any purpose.
bit 7 - 0 : not used.
5.1.12 PCI POWER MANAGEMENT CAPABILITY REGISTER ( PPMC ) ( 47h-44h )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
000 00 00 0
PME_Support
D2_Support
D1_Support
AUX_I
DSI
Auxiliary Power Source
PME Clock
Version
Next Pointer
Capability ID
bit 31- 27 : PME_Support, read only indicates the power states in which the function may assert LANWAKE pin.
bit 31 ---- PME_D3cold (value=1)
bit 30 ---- PME_D3warm (value=1)
bit 29 ---- PME_D2 (value=1)
bit 28 ---- PME_D1 (value=1)
bit 27 ---- PME_D0 (value=1)
bit 26 : D2 mode support, read only, set to 1.
bit 25 : D1 mode support, read only, set to 1.
bit 24-22 : AUX_I bits. Auxiliary current field, set to 100.
bit 21 : DSI, read only, set to 0.
bit 20 : Auxiliary power source, set to 1. This bit only valid when bit 15 is a '1'.
bit 19 : PME Clock, read only, set to 0.
bit 18-16 : PCI power management version, set to 001, read only.
bit 15-8 : Next Pointer, all bits set to 0.
bit 7-0 : Capability ID, read only, a 1 indicates that the data structure currently being pointed to is the PCI power
management data structure.
P/N:PM0719
REV. 0.1, FEB. 05, 2001
11
11 Page | ||
| Páginas | Total 40 Páginas | |
| PDF Descargar | [ Datasheet MX98715AEC-D.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MX98715AEC-C | SINGLE CHIP FAST ETHERNET NIC CONTROLLER - CRYSTAL VERSION | Macronix International |
| MX98715AEC-D | SINGLE CHIP FAST ETHERNET NIC CONTROLLER | Macronix International |
| MX98715AEC-E | SINGLE CHIP FAST ETHERNET NIC CONTROLLER - ENHANCED VERSION | Macronix International |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |