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PDF MX98715 Data sheet ( Hoja de datos )
| Número de pieza | MX98715 | |
| Descripción | SINGLE CHIP FAST ETHERNET NIC CONTROLLER - CRYSTAL VERSION | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MX98715 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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ADVANCED INFORMATION
MX98715AEC-C
1. FEATURES
SINGLECHIPFASTETHERNETNICCONTROLLER
-CRYSTALVERSION
• A single chip solution integrates 100/10 Base-T fast
Ethernet MAC, PHY and PMD.
• Microsoft PC97, 98, 99 and Novell 4.11/5.0 certified.
• Support DMI 2.0 management.
• Support Intel PXE remote boot device.
• Fully comply to IEEE 802.3u specification.
• Operates over 100 meters of STP and category 5 UTP
cable.
• Fully comply to PCI spec. 2.1 with clock frequency up
to 33MHz.
• Fully comply to Advanced Configuration and Power
Interface (ACPI) Rev 1.1
• Fully comply to PCI Bus Power Management Inter-
face spec. Rev 1.1
• Support full and half duplex operations in both 100
Base-TX and 10 Base-T mode.
• Supports 3 kinds of wake up events defined in Net-
work Device Class Power Management Spec 1.0.
Including:
- Magic PacketTM
- Link Change(link-on)
- Wake Up Frame
• Supports IEEE802.3x Frame Based Flow Control
scheme in full duplex mode.
• Supports early interrupt on both transmit and receive
operations.
• 100/10 Base-T NWAY auto negotiation function
• Large on-chip FIFOs for both transmit and receive
operations without external local memory
• Bus master architecture with linked host buffers deliv-
ers the most optimized performance
• 32-bit bus master DMA channel provides ultra low
CPU utilization, best fit in server and windows appli-
cation.
• Proprietary Adaptive Network Throughput Control
(ANTC) technology to optimize data integrity and
throughput
• Support up to 64K bytes boot ROM interface
• Three levels of loopback diagnositic capability
• Support a variety of flexible address filtering modes
with 16 CAM address and 128 bits hash
• MicroWire interface to EEPROM for customer's IDs
and configuration data
• Single +5V power supply, CMOS technology, 128-pin
PQFP package/LQPF package
2. GENERAL DESCRIPTIONS
The MX98715AEC-C controller is an IEEE802.3u com-
pliant single chip 32-bit full duplex, 10/100Mbps highly
integrated Fast Ethernet combo solution, designed to
address high performance local area networking (LAN)
system application requirements.
MX98715AEC-C's PCI bus master architecture delivers
the optimized performance for future high speed and pow-
erful processor technologies. In other words, the
MX98715AEC-C not only keeps CPU utilization low while
maximizing data throughput, but it also optimizes the
PCI bandwidth providing the highest PCI bandwidth uti-
lization. To further reduce maintenance costs the
MX98715AEC-C uses drivers that are backward com-
patible with the original MXIC MX98713 series control-
lers.
The MX98715AEC-C contains a PCI local bus glueless
interface, a Direct Memory Access (DMA) buffer man-
agement unit, an IEEE802.3u-compliant Media Access
Controller (MAC), large Transmit and Receive FIFOs, and
( Magic packet technology is a trademark of advanced Micro De-
vice Corp. )
an on-chip 10 Base-T and 100 Base-TX transceiver sim-
plifying system design and improving high speed signal
quality. Full-duplex operation are supported in both 10
Base-T and 100 Base-TX modes that increases the
controller's operating bandwidth up to 200Mbps.
Equipped with intelligent IEEE802.3u-compliant auto-
negotiation, the MX98715AEC-C-based adapter allows
a single RJ-45 connector to link with the other
IEEE802.3u-compliant device without re-configuration.
In MX98715AEC-C, an innovative and proprietary de-
sign "Adaptive Network Throughput Control" (ANTC) is
built-in to configure itself automatically by MXIC's driver
based on the PCI burst throughput of different PCs. With
this proprietary design, MX98715AEC-C can always
optimize its operating bandwidth, network data integrity
and throughput for different PCs.
The MX98715AEC-C features Remote-Power-On and Re-
mote-Wake-Up capability and is compliant with the Ad-
vanced Configuration and Power Interface version 1.0
P/N:PM0655
REV. 0.3, MAY. 04, 2000
1
1 page  
MX98715AEC-C
Pin Name Type
LED1
O
VDD
I
GND
I
Pin No
128 Pin Function and Driver
80 Programmable LED pin 1:
CSR9.29=1 Set the LED as Link/Activity LED.
CSR9.29=0 Set the LED as Good Link LED.
Default is Good Link LED after reset.
8,21,30,43, Power pins.
49,74,81,84,
88,90,93,96,
103,106,108,
121
2,5,11,16,27 Ground pins.
34,40,46,50
75,82,87
89,94,95,99
104,105,107
109,118,123,
126
P/N:PM0655
REV. 0.3, MAY. 04, 2000
5
5 Page 
MX98715AEC-C
5.1.13 PCI POWER MANAGEMENT COMMAND AND STATUS REGISTER ( PPMCSR ) ( 4Bh-48h )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
000 00 0
Data
Bridge Extension Support
PME_Status
Data_Scale
Data_Select
PME_EN
Reserved
Power State
bit 1-0 : Power_State, read/write, D0 mode is 00, D1 mode is 01, D2 mode is 10, D3 hot mode is 11.
bit7-2 : all 0. Reserved.
bit8 : PME_EN, set 1 to enable LANWAKE. Set 0 to disable LANWAKE assertion.
bit 12-9 : Data_Select for report in the Data register located at bit 31:24.
bit 14-13 : Data_Scale, read only.
bit 15 : PME_Status independent of the state of PME_EN.
When set, indicates a assertion of LANWAKE pin. (support D3 cold).
Write 1 to clear the LANWAKE signal. Write 0, no effect.
bit 21-16 : Reserved.
bit 22 : B2_B3#, B2_B3 support for D3 hot, meaningful only if BPCC_EN = 1, read only.
bit 23 : BPCC_EN, Bus Power/Clock Control Enable, read only.
bit 31-24 : Data, read only.
P/N:PM0655
REV. 0.3, MAY. 04, 2000
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MX98715.PDF ] | |
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