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PDF MX97103FC Data sheet ( Hoja de datos )
| Número de pieza | MX97103FC | |
| Descripción | ISDN S/T-PCI TRANSCEIVER | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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PRELIMINARY
MX97103
ISDN S/T-PCI TRANSCEIVER
FEATURE
• Single chip solution for ISDN PC card with PCI inter-
face
• Supports full duplex 2B+D ISDN S/T transceiver ac-
cording to ITU I.430
• Integrate S-interface, D & B channel protocol control-
lers, and PCI controller
• 32-bit PCI bus interface
• Each B channel has 2x64 byte FIFO for each direction
• D channel has 2x32 byte FIFO for each direction
• EEPROM interface for loading vendor-specific data
• One programmable LED
• Comply to ACPI Rev 1.0
• 0.5u CMOS
• 100-pin PQFP package
GENERAL DESCRIPTION
MX97103 is a single chip solution for ISDN-S connec-
tion on PCI bus. It integrates S-transceiver, D and B
channel protocol controllers, and PCI interface.
It can be divided into the following major functional blocks
: analog front end, layer 1 function, GCI interface. LAPD
controller, B channel HDLC controllers, EEPROM inter-
face and PCI interface. The important function of each
major block will be described below.
According to ITU 1.430 spec. the S/T interface is a 4-
wire interface. Among them, 2 wires are used for trans-
mitting, and the other two are for receiving. The wiring
configurations include short passive bus, extended pas-
sive bus and point-to-point connection. For short pas-
sive bus, the operation distance is from 100m to 200m,
and the TEs(max 8)can be connected at random points
along the full length of the cable. For extended passive
bus, TEs connect to the cable at the far end from the NT.
The total length would be at least 500m and a differen-
tial distance between TE connection points is of 25 to
50m. For point-to-point connection, the cable length can
be 1km.
The analog front end deals with the signals transmitted
to and received from the wiring cable. It accepts the
digital data from layer 1 block and converts them into
appropriate signals to be sent out to the wire, and it also
receive the attenuated and distorted signal from the wire
and recover them to be processed by layer 1 block.
The layer 1 block comprises of PDLL, DAC, RT and MFC
functions. DPLL's function is to establish S/T frame syn-
chronization. DAC resolves the contention issue for
differnet TE accessing D channel at the same time. RT
deals with the receiving S/T data extraction and put out
the transmitted data at the corrent time slot. MFC is the
multiframing S and Q channel control block.
GCI is the digital bus for the IC. It can accomodate 8
GCI-compatible devices. This block converts the frame
between GCI and S/T interface.
LAPD block relieves the microprocessor of the duty to
generate HDLC frame on the D channel. It can gener-
ate flag, CRC, address and control field automatically.
And it can generate S-frame for HDLC protocol. It con-
tains 2 FIFO of 2x32 byte each to facilitate the D packet
transmission and reception.
Two B channel HDLC controllers can handle tasks like
flag and CRC generation, zero insertion and deletion.
For each direction a 2x64 byte FIFO is provided to buffer
the data.
The EEPROM interface is used to load specific vendor
information after system hardware reset. Vendor ID and
device ID can be load to distinguish different products.
If EEPROM is not used, default values will be set.
The PCI interface enables the chip attached to PCI bus
directly without any glue logic. The bus speed can be
from 25MHz to 33MHz.
P/N:PM0564
REV. 1.0, FEB. 23, 1999
1
1 page  
MX97103
DC CHARACTERISTICS
PCI BUS D.C SPECS
PCI System signals
CLK, RST#
PCI Shared signals
AD[31:0](t/s), CBE[3:0]#(t/s), FRAME#(s/t/s), TRDY#(s/t/s), IDSEL(in), IRDY#(s/t/s), STOP#(s/t/s),
DEVSEL#(s/t/s), PAR(t/s), PERR#(s/t/s), INTA#(o/d), SERR#(s/t/s)
Temperature from 0 to 70°C; VDD=5V±5%, VSS=0V, AVSS=0V
SYMBOL PARAMETER
CONDITIONS MIN. VALUE
VIL L-input voltage
VIH H-input voltage
2.0V
VOL L-output voltage
IOL1=3mA
IOL2=6mA
VOH
H-output voltage
IOH=-2mA
2.4V
IIL L-input current
VIN=0.5V
IIH H-input current
VIN=2.7V
CI/O
Input/output capacitance at 1MHz
CCLK
CLK input capacitance
at 1MHz
CL Load capacitance
MAX. VALUE
0.8V
5.4V
0.45V
NOTES
1
-70uA
70uA
10pF
17pF
50pF
NOTE:
1. IOL2 applies to signals with external pull-ups: FRAME#, TRDY#, IRDY#, STOP#, DEVSEL#
GCI BUS & EEPROM INTERFACE D.C. SPECS
GCI signals:
BCL, DCL, DD, DU, FSC.SDS1, SDS2
EEPROM signals:
EECS, EECK, EEDI, EEDO
SYMBOL PARAMETER
VIL L-input voltage
VIH H-input voltage
VOL L-output voltage
VOH
H-output voltage
CONDITIONS
IOL1=2mA
IOL2=7mA
IOH=-400uA
NOTE:
1. IOL2 is for DD only.
MIN. VALUE
2.0V
2.4V
MAX. VALUE
0.8V
5.4V
0.45V
NOTES
1
P/N:PM0564
REV. 1.0, FEB. 23, 1999
5
5 Page 
MX97103
TEST CIRCUIT
To test digital function separately, DTMC[TMODE] can be set to enable the stimulus inputs from test1~4 pins.
PIN DTMC SP2 SP1 SP0 I/O SIGNAL DESCRIPTION
TEST1 1
X X X I XRAMI1 test RAMI1 input signal
TEST2 1
X X X I XRAMI2 test RAMI2 input signal
TEST3 1
X X X I XZC
test ZC input signal
TEST4 1
X X X I XI0N
test I0N input signal
TEST1 0
0 0 0 O ARAMI1 RAMI1 from analog module
TEST2 0
0 0 0 O ARAMI2 RAMI2 from analog module
TEST3 0
0 0 0 O AZC
ZC from analog module
TEST4 0
0 0 0 O SAMP SAMP from analog module
TEST1 0
0 0 1 O S[0]
activation/deactivation state code
TEST2 0
0 0 1 O S[1]
TEST3 0
0 0 1 O S[2]
TEST4 0
0 0 1 O S[3]
TEST1 0
0 1 0 O MBAS1 TIC bus arbitration state code
TEST2 0
0 1 0 O MBAS2
TEST3 0
0 1 0 O CLS
D channel collision
TEST4 0
0 1 0 O AI0N I0N from analog module
TEST1 0
0 1 1 O RFN
layer sync.
For normal operation, DTMC should be set to 0. Test1~4 pins can be programmed to output internal signals for
monitoring purpose.
P/N:PM0564
REV. 1.0, FEB. 23, 1999
11
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