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PDF MX97102QC Data sheet ( Hoja de datos )
| Número de pieza | MX97102QC | |
| Descripción | ISDN S/T CONTROLLER | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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FEATURES
• Pin-to-Pin and Register-to-Register compatible with
Siemens 2186
• Full duplex 2B+D ISDN S/T Transceiver according to
CCITT I.430
• GCI digital interface
• 3 types of 8-bit CPU interface
• Receive timing recovery with adaptively switched
thresholds
• E-channel Monitoring
MX97102
ISDN S/T CONTROLLER
• Programmable SDS1,SDS2
• D-channel access control
• LAPD(HDLC) support with FIFO(2x64) buffers
• Activation/Deactivation
• Multiframing with S and Q bit access
• CPU access to B and IC channels
• Watchdog timer
• Package types : P-LCC-44, P-LQFP-64
GENERAL DESCRIPTIONS
MX97102 implements the 4-wire S/T interface used to
link voice/data terminals to an ISDN. It is designed for
the user site of the ISDN-basic access, two 64kbit/s B
channels and a 16kbit/s D channel.
MX97102 can be mainly divided into three portions ac-
cording to their interfaces. Except these three interface
functions, it also provides the LAPD controller which
handles the HDLC packets of the ISDN D-channel for
the associated microprocessor.
The first, S/T interface controller, provides all electrical
and logical functions of the S/T interface, such as S/T
transceiver, activation/deactivation, timing recovery,
multiframe S and Q channels, and D-channel access
and priority control for communicating with remote
equipments.
The Second is the microprocessor interface controller
which offers the registers compatible with Siemens
PSB2186, provides three types of microprocessor in-
terface, such as Motorola bus mode, Intel multiplexed
mode and Intel non-multiplexed mode.
The last portion is the GCI interface controller which is
used to connect different voice/data application mod-
ules for local digital data exchangements.
PIN CONFIGURATION
44-PLCC
64-PLQFP
PSDS1
PSDS2
PRST
PA5(EAW)
VSSD
PDCL
PFSC1
NC
VSSD
ECHO
PA4
6
7
12
17
18
1 44
MX97102
23
40
39 PRDN(DS)
PWRN(R/W)
PCSN
PALE
PIDP1
34 PIDP0
PSX2
PSX1
VDD
NC
29 NC
28
NC
PA2
PA1
PSDS1
PSDS2
PRST
PA5(EAW)
NC
VSSD
PDCL
PFSC1
NC
VSSD
ECHO
PA4
PA3
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
MX97102
32 NC
31 NC
30 PA0
29 PRDN(D5)
28 PWRN(R/W)
27 PCSN
26 PALE
25 PIDP1
24 PIDP0
23 PSX2
22 PSX1
21 VDD
20 NC
19 NC
18 NC
17 NC
P/N:PM0473
REV. 2.5, SEP. 05, 2000
1
1 page  
MX97102
DC CHARACTERISTICS
TABLE 3: DC CHARACTERISTICS
Temperature from 0 to 70°C; VDD = 5V±5%, VSSA = 0V, VSSD = 0V
Symbol Parameter
Conditions
Min. Value
VIL L-input voltage
-0.4
VIH H-input voltage
2.0
VOL L-output voltage
IOL= 2mA
VOL1 L-output voltage (IDP0) IOL= 7mA
VOH H-output voltage
IOH= -400uA
2.4
VOH H-output voltage
IOH= -100uA
VDD-0.75
ILI Input leakage current 0<VIN<VDD to 0V
Max. Value
0.8
VDD+0.4
0.45
0.45
Unit
V
V
V
V
V
V
±10
ILO Output leakage current 0<VOUT<VDD to 0V
±10 uA
ILIPD Input leakage current,
internal pull-down
0<VIN<VDD to 0V
120 uA
VX
IX
RX
VSR1
VTR
Absolute value of
RL = 50ohm
output pulse amplitude RL = 400ohm
(VSX2 - VSX1)
Transmitter out-
put current
RL = 5.6ohm
Transmitter out-
Inactive or during
put impedance
binary one
during binary zero
RL = 50ohm
Receiver output voltage IO < 5uA
Receiver threshold
Dependent on
voltage (VSR2 - VSR1) peak level
2.03
2.35
7.5
10
0
2.35
225
2.31
2.65 V
13.4
kohm
ohm
2.63
375
mA
V
mV
Remarks
All pins except
PSX1, PSX2,
PSR1, PSR2
All pins except
BCL, PSX1,2,
PSR1,2, PA0,
PA1, PA3, PA4
PA0, PA1, PA3,
PA4, BCL
PSX1, PSX2
PSR1, PSR2
P/N:PM0473
REV. 2.5, SEP. 05, 2000
5
5 Page 
MX97102
FSC1
125 us
IPD0
(DD)
CH0
CH1
B1 B2 MONO D CIO IC1 IC2 MON1 CI1
MR MX
MR MX
IPD1
(DU)
B1 B2 MONO D CIO IC1 IC2 MON1 CI1
MR MX
MR MX
SDS1
CH2
S/G A/B
BAC TAD
IDP0,1:768 kbit/s
DCL :1536 kHz
FSC1 :8 kHz
BCL :768 kHz bit clock
SDS1 :8kHz programmable data strobe signal for
selecting one or both B/IC channel(s)
Figure 6-1 Frame structure of GCI
The GCI interface is operated in the “open drain” mode
in order to takes advantage of the bus capability. In this
case pull-up resisters (1kohm-5kohm) are required on
PIDP0 and PIDP1.
GCI OFF Function
In GCI terminal mode (SPCR:SPM=0) the GCI inter-
face can be switched off for external devices via IOF bit
in ADF1 register. If IOF=1, the interface is switched off.
Thus, DCL, FSC1, IDP0/1 and BCL are high impedence.
GCI Direction Control
For test applications, the direction of IDP0 (DD) and
IDP1 (DU) can be reversed during certain time-slots
within the GCI frame. This is performed via the IDC bit
in the SQXR register. For normal operation SQXR:IDC
should be set to “ 0 ” .
GCI has the 12-byte frame structure consisting of chan-
nels 0, 1 and 2. (see figure 6-1 above)
- IDP0 carries the 2B+D channels from the S/T inter-
face, and the MONITOR 0 and C/I 0 channels coming
from the S/T controller;
- IDP1 carries the MONITOR 0 and C/I 0 channels to
the layer-1.
Channel 1 of GCI interface is used for internal commu-
nication in terminal applications. Two cases have to be
distinguished, according to whether the MX97102 is op-
erated as a master device or as a slave device.
P/N:PM0473
REV. 2.5, SEP. 05, 2000
11
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