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PDF 87C552 Data sheet ( Hoja de datos )
| Número de pieza | 87C552 | |
| Descripción | 80C51 8-bit microcontroller 8K/256 OTP/ 8 channel 10 bit A/D/ I2C/ PWM/ capture/compare/ high I/O | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
NOTICE
PLEASE SEE THE P87C552 DATA SHEET FOR NEW DESIGN-INS
87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM,
capture/compare, high I/O
Product specification
Supersedes data of 1998 Jan 19
IC20 Data Handbook
1998 May 01
Philips
Semiconductors
1 page  
Philips Semiconductors
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
Product specification
87C552
PIN DESCRIPTION
PIN NO.
MNEMONIC PLCC
QFP
VDD 2 72
STADC
3 74
PWM0
PWM1
EW
P0.0-P0.7
4
5
6
57-50
75
76
77
58-51
P1.0-P1.7
16-23
16-21
22-23
16-19
20
21
22
23
10-17
10-15
16-17
10-13
14
15
16
17
P2.0-P2.7
P3.0-P3.7
P4.0-P4.7
P5.0-P5.7
RST
XTAL1
XTAL2
VSS
PSEN
39-46
38-42,
45-47
24-31
24
25
26
27
28
29
30
31
7-14
7-12
13, 14
68-62,
1
15
18-20,
23-27
18
19
20
23
24
25
26
27
80, 1-2
4-8
80, 1-2
4-6
7, 8
71-64,
9
35 32
34
36, 37
47
31
34-36
48
TYPE
NAME AND FUNCTION
I Digital Power Supply: +5V power supply pin during normal operation, idle and
power-down mode.
I Start ADC Operation: Input starting analog to digital conversion (ADC operation can also
be started by software).
O Pulse Width Modulation: Output 0.
O Pulse Width Modulation: Output 1.
I Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode.
I/O Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written
to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application it uses strong internal pull-ups when emitting 1s. Port 0 is also used to input
the code byte during programming and to output the code byte during verification.
I/O Port 1: 8-bit I/O port. Alternate functions include:
I/O (P1.0-P1.5): Quasi-bidirectional port pins.
I/O (P1.6, P1.7): Open drain port pins.
I CT0I-CT3I (P1.0-P1.3): Capture timer input signals for timer T2.
I T2 (P1.4): T2 event input.
I RT2 (P1.5): T2 timer reset signal. Rising edge triggered.
I/O SCL (P1.6): Serial port clock line I2C-bus.
I/O SDA (P1.7): Serial port data line I2C-bus.
Port 1 is also used to input the lower order address byte during EPROM programming and
verification. A0 is on P1.0, etc.
I/O Port 2: 8-bit quasi-bidirectional I/O port.
Alternate function: High-order address byte for external memory (A08-A15). Port 2 is also
used to input the upper order address during EPROM programming and verification. A8 is
on P2.0, A9 on P2.1, through A12 on P2.4.
I/O Port 3: 8-bit quasi-bidirectional I/O port. Alternate functions include:
RxD(P3.0): Serial input port.
TxD (P3.1): Serial output port.
INT0 (P3.2): External interrupt.
INT1 (P3.3): External interrupt.
T0 (P3.4): Timer 0 external input.
T1 (P3.5): Timer 1 external input.
WR (P3.6): External data memory write strobe.
RD (P3.7): External data memory read strobe.
I/O Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include:
O CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with
timer T2.
O CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2.
I Port 5: 8-bit input port.
ADC0-ADC7 (P5.0-P5.7): Alternate function: Eight input channels to ADC.
I/O Reset: Input to reset the 87C552. It also provides a reset pulse as output when timer T3
overflows.
I Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the
internal clock generator. Receives the external clock signal when an external oscillator is
used.
O Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open-circuit
when an external clock is used.
I Digital ground.
O Program Store Enable: Active-low read strobe to external program memory.
1998 May 01
5
5 Page 
Philips Semiconductors
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
Product specification
87C552
AC ELECTRICAL CHARACTERISTICS1, 2
12MHz CLOCK 16MHz CLOCK
VARIABLE CLOCK
SYMBOL FIGURE
PARAMETER
MIN MAX MIN MAX
MIN
MAX
1/tCLCL
tLHLL
tAVLL
tLLAX
tLLIV
tLLPL
tPLPH
tPLIV
tPXIX
tPXIZ
tAVIV
tPLAZ
Data Memory
2
2
2
2
2
2
2
2
2
2
2
2
Oscillator frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
3.5 16
127 85 2tCLCL–40
28 8 tCLCL–55
48 28 tCLCL–35
234 150
4tCLCL–100
43 23 tCLCL–40
205 143 3tCLCL–45
145 83
3tCLCL–105
00
0
59 38
312 208
10 10
tCLCL–25
5tCLCL–105
10
tAVLL
3, 4 Address valid to ALE low
43 23 tCLCL–40
tRLRH
3 RD pulse width
400 275 6tCLCL–100
tWLWH
3 WR pulse width
400 275 6tCLCL–100
tRLDV
3 RD low to valid data in
252 148
tRHDX
3 Data hold after RD
00
0
tRHDZ
3 Data float after RD
97 55
tLLDV
3 ALE low to valid data in
517 350
tAVDV
3 Address to valid data in
585 398
tLLWL
3, 4 ALE low to RD or WR low
200 300 138 238 3tCLCL–50
tAVWL
3, 4 Address valid to WR low or RD low
203
120 4tCLCL–130
tQVWX
4 Data valid to WR transition
23
3
tCLCL–60
tDW 4 Data before WR
433 288 7tCLCL–150
tWHQX
4 Data hold after WR
33 13 tCLCL–50
tRLAZ
4 RD low to address float
00
tWHLH
3, 4 RD or WR high to ALE high
43 123 23 103 tCLCL–40
External Clock
tCHCX
5 High time3
20 20
20
tCLCX
5 Low time3
20 20
20
tCLCH
5 Rise time3
20 20
tCHCL
5 Fall time3
20 20
Serial Timing – Shift Register Mode4 (Test Conditions: Tamb = 0°C to +70°C; VSS = 0V; Load Capaciatnce = 80pF)
tXLXL
6 Serial port clock cycle time
1.0 0.75
12tCLCL
tQVXH
6 Output data setup to clock rising edge 700
492 10tCLCL–133
tXHQX
6 Output data hold after clock rising edge 50
8 2tCLCL–117
tXHDX
6 Input data hold after clock rising edge 0
0
0
tXHDV
6 Clock rising edge to input data valid
700 492
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. tCLCL = 1/fOSC = one oscillator clock period.
tCLCL = 83.3ns at fOSC = 12MHz.
tCLCL = 62.5ns at fOSC = 16MHz.
4. These values are characterized but not 100% production tested.
5tCLCL–165
2tCLCL–70
8tCLCL–150
9tCLCL–165
3tCLCL+50
0
tCLCL+40
20
20
10tCLCL–133
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
1998 May 01
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet 87C552.PDF ] | |
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