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PDF NM24C32 Data sheet ( Hoja de datos )
| Número de pieza | NM24C32 | |
| Descripción | 32K-Bit Extended 2-Wire Bus Interface Serial EEPROM with Write Protect | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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PRELIMINARY
March 1999
NM24C32
32K-Bit Extended 2-Wire Bus Interface
Serial EEPROM with Write Protect
General Description:
The NM24C32 devices are 32,768 bits of CMOS nonvolatile
electrically erasable memory. These devices offer the designer
different low voltage and low power options, and they conform to
all specifications in the Extended IIC 2-wire protocol. Furthermore,
they are designed to minimize device pin count and simplify PC
board layout requirements.
The upper half of the memory can be disabled (Write Protection)
by connecting the WP pin to VCC. This section of memory then
becomes ROM.
This communication protocol uses CLOCK (SCL) and DATA I/O
(SDA) lines to synchronously clock data between the master (for
example a microprocessor) and the slave EEPROM device(s).
Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability, and low power con-
sumption.
Features:
s Extended operating voltage 2.7V – 5.5V
s 400 KHz clock frequency (F) at 2.7V - 5.5V
s 200µA active current typical
10µA standby current typical
1µA standby typical (L)
0.1µA standby typical (LZ)
s IIC compatible interface
– Provides bidirectional data transfer protocol
s 32 byte page write mode
– Minimizes total write time per byte
s Self timed write cycle
Typical write cycle time of 6ms
s Hardware write protect for upper block
s Endurance: 1,000,000 data changes
s Data retention greater than 40 years
s Packages available: 8-pin SO, 8-pin DIP
s Low VCC programming lockout (3.8V - on Standard VCC
devices only).
Block Diagram
VCC
WP
SDA
WRITE
LOCKOUT
START
STOP
LOGIC
START CYCLE
H.V. GENERATION
TIMING &CONTROL
SCL
A2
A1
A0
SLAVE ADDRESS
REGISTER &
COMPARATOR
CONTROL
LOGIC
LOAD
INC
WORD
ADDRESS
COUNTER
XDEC
E2PROM
ARRAY
R/W
YDEC
CK
DIN
DATA REGISTER
DOUT
© 1999 Fairchild Semiconductor Corporation
NM24C32 Rev. C.2
1
DS500073-1
www.fairchildsemi.com
1 page  
Bus Timing
SCL
tF
tLOW
tHIGH
SDA
tSU:STA
tHD:STA
tHD:DAT
IN
SDA
OUT
tAA
BACKGROUND INFORMATION (IIC Bus)
As mentioned, the IIC bus allows synchronous bidirectional commu-
nication between Transmitter/Receiver using the SCL (clock) and
SDA (Data I/O) lines. All communication must be started with a valid
START condition, concluded with a STOP condition and acknowl-
edged by the Receiver with an ACKNOWLEDGE condition.
In addition, since the IIC bus is designed to support other devices
such as RAM, EPROM, etc., the device type identifier string, or
slave address, must follow the START condition. For EEPROMs,
the first 4-bits of the slave address is '1010'. This is then followed
by the device selection bits A2, A1 and A0.The final bit in the slave
address determines the type of operation performed (READ/
WRITE). A "1" signifies a READ while a "0" signifies a WRITE. The
slave address is then followed by two bytes that define the word
address, which is then followed by the data byte.
The EEPROMs on the IIC bus may be configured in any manner
required, providing the total memory addressed does not exceed
4M bits in the Extended IIC protocol. EEPROM memory address-
ing is controlled by hardware configuring the A2, A1, and A0 pins
(Device Address pins) with pull-up or pull-down resistors. ALL
UNUSED PINS MUST BE GROUNDED (tied to VSS).
Addressing an EEPROM memory location involves sending a
command string with the following information:
[DEVICE TYPE]-[DEVICE ADDRESS]-[PAGE BLOCK AD-
DRESS]-[BYTE ADDRESS]
tR
tLOW
tSU:DAT
tSU:STO
tDH
tBUF
Word
Page
Master
Slave
Transmitter
Receiver
DS500073-3
Definitions
8 bits (byte) of data
32 sequential addresses (one byte
each) that may be programmed during
a "Page Write" programming cycle.
Any IIC device CONTROLLING the
transfer of data (such as a microcon-
troller).
Device being controlled (EEPROMS
are always considered Slaves).
Device currently SENDING data on the
bus (may be either a Master or Slave).
Device currently receiving data on the
bus (Master or Slave).
Pin Description
SERIAL CLOCK (SCL)
The SCL input is used to clock all data into and out of the device.
SERIAL DATA (SDA)
SDA is a biderectional pin used to transfer data into and out of the
device. It is an open drain output and may be wire-ORed with any
number of open drain or open collector outputs.
NM24C32 Rev. C.2
5 www.fairchildsemi.com
5 Page 
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
87 65
0.228 - 0.244
(5.791 - 6.198)
0.010 - 0.020 x 45°
(0.254 - 0.508)
0.150 - 0.157
(3.810 - 3.988)
8° Max, Typ.
All leads
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.04
(0.102)
All lead tips
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
12 34
Lead #1
IDENT
0.053 - 0.069
(1.346 - 1.753)
0.014
(0.356)
0.050
(1.270)
Typ
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.014 - 0.020 Typ.
(0.356 - 0.508)
Molded Small Out-Line Package (M8)
Order Number NM24C32xxxM8 or NM24C32xxxEM8
Package Number M08A
NM24C32 Rev. C.2
11 www.fairchildsemi.com
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet NM24C32.PDF ] | |
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