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PDF NLAS44599MNR2 Data sheet ( Hoja de datos )
| Número de pieza | NLAS44599MNR2 | |
| Descripción | Low Voltage Single Supply Dual DPDT Analog Switch | |
| Fabricantes | ON | |
| Logotipo |  |
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NLAS44599
Low Voltage Single Supply
Dual DPDT Analog Switch
The NLAS44599 is an advanced dual−independent CMOS double
pole−double throw (DPDT) analog switch fabricated with silicon
gate CMOS technology. It achieves high speed propagation delays
and low ON resistances while maintaining CMOS low power
dissipation. This DPDT controls analog and digital voltages that may
vary across the full power−supply range (from VCC to GND).
The device has been designed so the ON resistance (RON) is much
lower and more linear over input voltage than RON of typical CMOS
analog switches.
The channel select input is compatible with standard CMOS outputs.
The channel select input structure provides protection when
voltages between 0 V and 5.5 V are applied, regardless of the supply
voltage. This input structure helps prevent device destruction caused
by supply voltage − input/output voltage mismatch, battery backup,
hot insertion, etc.
The NLAS44599 can also be used as a quad 2−to−1 multiplexer−
demultiplexer analog switch with two Select pins that each controls
two multiplexer−demultiplexers.
• Channel Select Input Over−Voltage Tolerant to 5.5 V
• Fast Switching and Propagation Speeds
• Break−Before−Make Circuitry
• Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
• Diode Protection Provided on Channel Select Input
• Improved Linearity and Lower ON Resistance over Input Voltage
• Latch−up Performance Exceeds 300 mA
• ESD Performance: Human Body Model; > 2000 V,
Machine Model; > 200 V
• Chip Complexity: 158 FETs
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MARKING
DIAGRAMS
16
1
QFN−16
MN SUFFIX
CASE 485G
AS
4459
ALYW
Current
Part Marking
16
1
C
ALYW
Previous
Part Marking*
*Previous releases of this device may be marked as
shown in this diagram.
16
1
TSSOP−16
DT SUFFIX
CASE 948F
16 9
NLAS
4459
ALYW
18
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2004
December, 2004 − Rev. 12
1
Publication Order Number:
NLAS44599/D
1 page  
NLAS44599
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
Guaranteed Maximum Limit
Symbol
Parameter
Test Conditions
VCC VIS *555C to 255C
t855C
t1255C
(V) (V) Min Typ* Max Min Max Min Max Unit
tON Turn−On Time
(Figures 12 and 13)
RL = 300 W, CL = 35 pF 2.5 2.0 5 23 35 5 38 5 41 ns
(Figures 5 and 6)
3.0 2.0 5 16 24 5 27 5 30
4.5 3.0 2 11 16 2 19 2 22
5.5 3.0 2 9 14 2 17 2 20
tOFF Turn−Off Time
(Figures 12 and 13)
RL = 300 W, CL = 35 pF 2.5 2.0
(Figures 5 and 6)
3.0 2.0
4.5 3.0
5.5 3.0
1
1
1
1
7 12 1 15 1 18 ns
5 10 1 13 1 16
4 6 1 9 1 12
3 5 1 8 1 11
tBBM
Minimum Break−Before−Make
VIS = 3.0 V (Figure 4)
2.5 2.0 1 12
1
1
ns
Time
RL = 300 W, CL = 35 pF 3.0 2.0 1 11 1 1
4.5 3.0 1 6 1 1
5.5 3.0 1 5 1 1
CIN
CNO or CNC
CCOM
C(ON)
Maximum Input Capacitance, Select Input
Analog I/O (switch off)
Common I/O (switch off)
Feedthrough (switch on)
*Typical Characteristics are at 25°C.
Typical @ 25, VCC = 5.0 V
8
10
10
20
pF
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
Symbol
Parameter
BW Maximum On−Channel −3dB
Bandwidth or Minimum Frequency
Response (Figure 11)
VONL Maximum Feedthrough On Loss
VISO Off−Channel Isolation (Figure 10)
Q Charge Injection Select Input to
Common I/O (Figure 15)
THD
VCT
Total Harmonic Distortion THD +
Noise (Figure 14)
Channel−to−Channel Crosstalk
Condition
VIN = 0 dBm
VIN centered between VCC and GND
(Figure 7)
VIN = 0 dBm @ 100 kHz to 50 MHz
VIN centered between VCC and GND
(Figure 7)
f = 100 kHz; VIS = 1 V RMS
VIN centered between VCC and GND
(Figure 7)
VIN = VCC to GND, FIS = 20 kHz
tr = tf = 3 ns
RIS = 0 W, CL = 1000 pF
Q = CL * DVOUT
(Figure 8)
FIS = 20 Hz to 100 kHz, RL = Rgen = 600 W, CL = 50 pF
VIS = 5.0 VPP sine wave
f = 100 kHz; VIS = 1 V RMS
VIN centered between VCC and GND
(Figure 7)
VCC Typical
V 255C Unit
3.0 145 MHz
4.5 170
5.5 175
3.0 −3 dB
4.5 −3
5.5 −3
3.0 −93 dB
4.5 −93
5.5 −93
pC
3.0 1.5
5.5 3.0
%
5.5 0.1
dB
5.5 −90
3.0 −90
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5
5 Page 
NLAS44599
PACKAGE DIMENSIONS
QFN−16
MN SUFFIX
CASE 485G−01
ISSUE B
D
ÎÎÎÎÎÎPIN 1
LOCATION
A
B
E
0.15 C
0.15 C
TOP VIEW
0.10 C
16 X 0.08 C
(A3)
SIDE VIEW
A
SEATING
PLANE
A1 C
16X L
NOTE 5
16X K
D2
e
58
EXPOSED PAD
49
E2
e
1 12
16 13
16X b
0.10 C A B BOTTOM VIEW
0.05 C NOTE 3
0.575
0.022
3.25
0.128
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
MILLIMETERS
DIM MIN MAX
A 0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b 0.18 0.30
D 3.00 BSC
D2 1.65 1.85
E 3.00 BSC
E2 1.65 1.85
e 0.50 BSC
K 0.20 −−−
L 0.30 0.50
SOLDERING FOOTPRINT
3.25
0.128
0.30
0.012
EXPOSED PAD
1.50
0.059
0.30
0.50 0.012
ǒ Ǔ0.02
SCALE 10:1
mm
inches
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11
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