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PDF NJU7001 Data sheet ( Hoja de datos )
| Número de pieza | NJU7001 | |
| Descripción | LOW VOLTAGE C-MOS OPERATIONAL AMPLIFIER | |
| Fabricantes | New Japan Radio | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de NJU7001 (archivo pdf) en la parte inferior de esta página. Total 58 Páginas | ||
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NJU6682
PRELIMINARY
160-common x 132-segment
DOT MATRIX LCD DRIVER FOR 4 GRAY SCALE
sGENERAL DESCRIPTION
The NJU6682 is a bit map LCD driver to display graphics or characters.
It contains 84,480 bits display data RAM, microprocessor interface circuits,
instruction decoder, and 160-common and 132-segment drivers.
The bit image data is transferred to the internal display data RAM by
serial interface or 8-bit/16-bit parallel interface.
The NJU6682 features 4-gray scale function which creates 4 types gray
scale (for example : white/light gray/dark gray/black) or black & white with
displays 160 x 132 dots graphics or 8-caracter 10line by 16 x 16 dots
characters.
It oscillates by built-in OSC circuit without any external components.
Furthermore, the NJU6682 features Partial Display Function which
creates up to 2 blocks of active display area and optimizes duty cycle ratio.
This function sets optimum boosted voltage by the combination with both
of programmable voltage booster circuit and electrical variable resister. As
result, it reduces the operating current.
The operating voltage from 2.4V to 3.3V and low operating current are
useful for small size battery operating items.
sPACKAGE OUTLINE
NJU6682CH
sFEATURES
qDirect Correspondence between Display Data RAM and LCD Pixel
qDisplay Data RAM - 84,480 bits ;( 160-Com x 132-Seg) x 2-area ) x 2bit
….2 times over than display size
qDisplay Method – Monochrome 4-Gray Scale / Black & White
qPartial Display Function
( 2 blocks of active display area and automatic duty cycle ratio selection )
qVariable RAM Mapping
– The display screen can be composed from the RAM area in a maximum of 8 blocks not to continue.
qEasy Vertical Scroll by the variable start line address and over size display data RAM
(This function doesn’t work in Variable RAM Mapping mode )
qLCD drivers – 160-common and 132-segment
qDirect 8-bit / 16-bit Microprocessor interface for both of 68 type and 80 type MPU
qSerial Interface
qProgrammable Bias selection ; 1/4, 1/5, 1/6, 1/7, 1/8, 1/9, 1/10, 1/11, 1/12, 1/13, 1/14 bias
qCommon Driver Order Assignment by mask option
Version C0 to C159( Pin Name )
NJU6682A
COM0 to COM159
NJU6682B
COM159 to COM0
qUseful Instruction Set
Display Data Read/Write, Display ON/OFF, Z-Address Set, X-Address Set, Y-Address Set, Status Read, Normal or
Inverse ON/OFF, Static Drive ON/OFF, Partial Display, n-Line Inverse, EVR Resister Set, Variable RAM Mapping
Mode, Gray Scale Level Select, Bias Select, Voltage Converter Multiple Select ( 7-times maximum ), Read Modify
Write, Reset ,Internal Power Supply, Driver Outputs ON/OFF, Power Save, ADC Select, Display Mode Select, 8-bit /
16-bit Buss Select, etc.
qPower Supply Circuit for LCD; Programmable Booster Circuits( 7-time maximum ), Regulator, Voltage Follower x 4
qPrecision Electrical Variable Resistance
qLow Power Consumption
T.B.D ( typ. )
qOperating Voltage
2.4 to 3.3 V
qLCD Driving Voltage
6.0 to 18.0V
qPackage Outline
Bumped Chip / TCP
qC-MOS Technology
MAY 2000 Ver-1.3
1 page  
NJU6682
PAD No.
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
Terminal
C151
C152
C153
C154
C155
C156
C157
C158
C159
S131
S130
S129
S128
S127
S126
S125
S124
S123
S122
S121
S120
S119
S118
S117
S116
S115
S114
S113
S112
S111
S110
S109
S108
S107
S106
S105
S104
S103
S102
S101
S100
S99
S98
S97
S96
S95
S94
S93
S92
S91
X(um)
-330
-390
-450
-510
-570
-630
-690
-750
-810
-870
-930
-990
-1050
-1110
-1170
-1230
-1290
-1350
-1410
-1470
-1530
-1590
-1650
-1710
-1770
-1830
-1890
-1950
-2010
-2070
-2130
-2190
-2250
-2310
-2370
-2430
-2490
-2550
-2610
-2670
-2730
-2790
-2850
-2910
-2970
-3030
-3090
-3150
-3210
-3270
Y(um)
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
PAD No.
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
Terminal
S90
S89
S88
S87
S86
S85
S84
S83
S82
S81
S80
S79
S78
S77
S76
S75
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
X(um)
-3330
-3390
-3450
-3510
-3570
-3630
-3690
-3750
-3810
-3870
-3930
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
-3975
Y(um)
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2517
2457
2397
2337
2277
2217
2157
2097
2037
1977
1917
1857
1797
1737
1677
1617
1557
1497
1437
1377
1317
1257
1197
1137
1077
1017
957
897
837
777
717
657
597
537
477
417
357
297
237
5 Page 
NJU6682
Functional Description
(1)Description for each blocks
1-1) Busy Flag (BF)
As for NJU6682, in case of the inner operation, busy flag (BF) doesn't accept an instruction except of "1". In the
status reed instruction, a busy flag is output by the D7 terminal. If cycle time (tcyc) is secured, to check this flag in
front of the instruction isn't necessary and the throughput of the CPU can be substantially improved.
1-2) X-Address Counter
The X-address counter is the 6 bit presettable counter which gives an address for the row of the display data RAM
as shown in figure 1 and is done in +1 increment by the execution of the display data read / write instruction. But,
when the X-address counter reaches the maximum of the exist address, the count locks by the X-address counter.
With to set X-address once again, as for the count lock of cancellation again this counter is independent with
Y-address register.
By the address inverse instruction(ADC), it is possible for X-address decoder to reverse correspondence relation
between X-address and segment output of display data RAM.
1-3)Z-Address counter
The Y-address counter generates an address to the display RAM direction of the line, it is reset when the inner FR
signal switching timing and count up synchronizes with common cycle of NJU6682.
1-4)Y-Address Register
Y-address register is which gives an address to the display data RAM direction of the line as shown in figure 1.
When replacing Y-address from the CPU and accessing to them, it does by the instruction of the set of Y-address.
1-5)Z-Address Register
Z-address register can be generally used for the scrolling of a screen, in addition to the display with the register
which sets the low address of the data RAM which corresponds to the display line ( being the best line generally ) of
COM0. It sets a display beginning line by setting the display beginning address of 9 bits in this register by the
instruction of the set of Z-address.
1-6)Display data RAM
Display data RAM is the bit map RAM which stores the data for the display which corresponds to the LCD pixel
and is composed of 84,480 bits. Each bit of the display data RAM corresponds to 2:1 in case of gray scale display to
each pixel of LCD and in case of Black and White display, it corresponds to 1:1. The relation between the display
data and the LCD in case of gray scale display is as follows.
The relation between Display data and LCD in Gray Scale Display
The Display RAM data : "00" = Gray Scale Level 0 ( setting by the gray scale level select )
The Display RAM data : "01" = Gray Scale Level 1 (
“
)
The Display RAM data : "10" = Gray Scale Level 2 (
“
)
The Display RAM data : "11" = Gray Scale Level 3 (
“
)
The relation between Display data and LCD in Black and White Display
In Positive Display : "1"=Turn-On Display,"0" =Turn-Off Display
In Negative Display: "1"=Turn-Off Display,"0" =Turn-On Display
When the Display method chooses 16 bit access by the gray scale display, because RAM area of X-address = 16
become 8 bits, lower 8bit (D7-D0) is ignored ( Figure 1-1 ). When the display method chooses 16 bit access by the
Black and White display, as for RAM area of X-address = 8 (Layer0) or 40 (Layer1) becomes 4-bits, lower 12 bit
(D11-D0) is ignored. The bus with in access to the Display Data RAM is 8-bit access an d 16-bit access with the 8-bit
/ 16-bit Bus Select instruction. The access can be chosen.
11 Page | ||
| Páginas | Total 58 Páginas | |
| PDF Descargar | [ Datasheet NJU7001.PDF ] | |
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