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PDF NJU6631A Data sheet ( Hoja de datos )
| Número de pieza | NJU6631A | |
| Descripción | 16-CHARACTER 1-LINE DOT MATRIX LCD CONTROLLER DRIVER | |
| Fabricantes | New Japan Radio | |
| Logotipo |  |
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NJU6631A
PRELIMINARY
16-CHARACTER 1-LINE DOT MATRIX
LCD CONTROLLER DRIVER
s GENERAL DESCRIPTION
The NJU6631A is a 1 Chip Dot Matrix LCD controller
driver for up to 16-character 1-line or 8-character 2-line
display.
It contains microprocessor interface circuits,
instruction decoder controller, character generator
ROM/RAM and common and segment drivers.
The bleeder resistance generates for LCD Bias
voltage internally.
The CR oscillator incorporates C and R, therefore no
external components for oscillation are required.
The microprocessor interface circuits which operate
2MHz frequency, can be connected directly to 4bit/8bit
microprocessor.
The character generator consists of 9,600 bits ROM
and 32 x 5 bits RAM. The standard version ROM is
coded with 192 characters including capital and small
letter fonts.
The 16-common and 40-segment drives up to 16-
character 1-line LCD panels which divided two common
electrode blocks.
The rectangle outlook is very applicable to COG or
Slim TCP.
s PACKAGE OUTLINE
NJU6631ACH
s FEATURES
q 16-character 1-line Dot Matrix LCD Controller Driver
q 4/8 Bit Microprocessor Direct Interface
q Display Data RAM
- 16 x 8 bits : Maximum 16-character 1-line Display
q Character Generator ROM - 9,600 bits : 240 Characters for 5 x 8 Dots
q Character Generator RAM - 32 x 5 bits : 4 Patterns(5 x 8 Dots)
q Microprocessor can access to Display Data RAM and Character Generator RAM
q High Voltage LCD Driver : 16-common / 40-segment
q Duty Ratio
: 1/16 Duty
q Number of Maximum Display Characters : 16-character
q Useful Instruction Set
Clear Display, Return Home, Display ON/OFF Cont, Cursor ON/OFF Cont, Display Blink,
Cursor Shift, Character Shift,
q Common and Segment driver Location order Select Function(Pin configuration mode A / mode B)
q Power On Initialize / Hardware Reset Function
q Bleeder Resistance On-chip
q Oscillation Circuit On-chip
q Low Power Consumption
q Operating Voltage --- +5V
q Package Outline --- Bumped Chip
q C-MOS Technology
31.Mar,2000
Ver.1
1 page  
NJU6631A
s FUNCTIONAL DESCRIPTION
(1) Description for each blocks
(1-1) Register
The NJU6631A incorporates two 8-bit registers, an Instruction Register (IR) and a Data Register (DR).
The Register (IR) stores instruction codes such as “Clear Display” and “Return Home”, and address data for
Display Data RAM (DD RAM) and Character Generator RAM (CG RAM). The MPU can write the instruction
code and address data to the Register (IR), but it cannot read out from the Register (IR).
The Register (DR) is a temporary stored register, the data stored in the Register (DR) is written into the DD
RAM or CG RAM and read out from the DD RAM or CG RAM.
The data in the Register (DR) written by the MPU is transferred automatically to the DD RAM or CG RAM by
internal operation.
When the address data for the DD RAM or CG RAM is written into the Register (IR), the addressed data in
the DD RAM or CG RAM is transferred to the Register (DR). By the MPU read out the data in the Register
(DR), the data transmitting process is performed completely.
After reading the data in the Register (DR) by the MPU, the next address data in the DD RAM or CG RAM is
transferred automatically to the Register (DR) to provide for the next MPU reading.
These two registers are selected by the selection signal RS as shown below :
Table 1. shows register operation controlled by RS and R/W signals.
Table 1. Register Operation
RS R/W Selected Register
Operation
00
01
10
11
Write
IR
Read busy flag (DB7) and address counter (DB0∼DB6)
DR Write (DR to DD RAM or CG RAM)
Read (DD RAM or CG RAM to DR)
(1-2) Busy Flag (BF)
When the internal circuits are in the operation mode, the busy flag is "1", and any instruction reading is
inhibited.
The busy flag (BF) is output at DB7 when RS="0" and R/W="1" as shown in table 1.
The next instruction should be written after busy flag (BF) goes to "0".
(1-3) Address Counter (AC)
The address Counter (AC) addressing the DD RAM and CG RAM.
When the address setting instruction is written into the Register (IR), the address information is transferred
from Register (IR) to counter (AC). The selection of either the DD RAM or CG RAM is also determined by this
instruction.
After writing (or reading) the display data to (or from) the DD RAM or CG RAM, the Counter (AC)
increments (or decrements) automatically.
The address data in the Counter (AC) is output from DB6∼DB0 when RS="0" and R/W="1" as shown in Table
1.
(1-4) Display Data RAM (DD RAM)
The display data RAM (DD RAM) consists of 16 x 8 bits, stores up to 16-character display data represented
in 8-bit code.
The DD RAM address data set in the address Counter (AC) is represented in Hexadecimal.
Higher order bit
Lower order bit
AC AC6 AC5 AC4 AC3 AC2 AC1 AC0
Hexadecimal
Hexadecimal
(Example) DD RAM address “08”
000100
08
0
5 Page 
NJU6631A
(1-7) Timing Generator
The timing generator generates a timing signals for the DD RAM, CG RAM, CG ROM and other internal
circuits operation.
RAM read timing for the display and internal operation timing for MPU access are separately generated, so
that they may not interfere with each other.
Therefore, when the data write to the DD RAM for example, there will be no undesirable influence, such as
flickering, in areas other than the display area.
(1-8) LCD Driver
LCD driver circuits consist of 16-common driver and 40-segment driver.
The 40 bits of character pattern data are shifted in the shift-register and latched when the 40 bits shift
performed completely. This latched data controls display driver to output LCD driving waveform.
(1-9) Cursor Blinking Control Circuit
This circuits controls cursor On/Off and cursor position character blinks.
The cursor or blinks appear in the digit residing at the DD RAM address set in the address counter (AC).
When the address counter is (04)H, a cursor position is shown as follows :
AC6 AC5 AC4 AC3 AC2 AC1 AC0
AC 0 0 0 0 1 0 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ←Display Position
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F ←DD RAM Address
(Hexadecimal)
Cursor Position
Note）The cursor or blinks appear when the address counter (AC) selects the CG RAM.
But the displayed the cursor and blink are meaningless.
If the AC storing the CG RAM address data, the cursor and blink are displayed in the meaningless
position.
11 Page | ||
| Páginas | Total 32 Páginas | |
| PDF Descargar | [ Datasheet NJU6631A.PDF ] | |
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