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PDF NJG1707PG1 Data sheet ( Hoja de datos )
| Número de pieza | NJG1707PG1 | |
| Descripción | 800MHz TDMA FRONT-END GaAs MMIC | |
| Fabricantes | New Japan Radio | |
| Logotipo |  |
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NJG1707PG1
800MHz TDMA FRONT-END GaAs MMIC
nGENERAL DESCRIPTION
NJG1707PG1 is a front-end IC for a digital cellular phone of
800MHz band. A 2x6 antenna switches and a low noise
amplifier are included.
The parallel control signals of three bits logic connect T/R
circuits to internal two antennas or external two antennas. The
termination ports with external matching circuits make low
interference between diversity antennas.
The ultra small & thin FFP32-G1 package is adopted.
nPACKAGE OUTLINE
NJG1707PG1
nFEATURES
•Ultra small & thin package
•Antenna Switch
lLow voltage operation
lLow current consumption
lLow insertion loss
lLow Adjacent Channel
Leakage Power
•Low Noise Amplifier
lLow voltage operation
lLow current consumption
lSmall signal gain
lLow noise figure
lHigh input IP3
FFP32-G1 (Mount Size: 4.5x4.5x0.85mm)
-2.5V (Tx only) and +3.5V
10uA typ. (Tx Mode, Pin=30dBm), 2uA typ. (Rx Mode, Pin=10dBm)
0.5dB typ. @(Tx-ANT1, Tx-EXT1) fin=960MHz, Pin=30dBm
-63dBc typ. @ VDD=+3.5V, VSS=-2.5V, fin=960MHz, Pin=30dBm
+2.7V typ.
+2.7mA typ.
17.5dB typ. @f=820MHz
1.4dB typ. @ f=820MHz
IIP3=-4.5dBm typ. OIP3=+13dBm typ. @f=820MHz+820.1MHz
nPIN CONFIGURATION
FFP32 Type
(Top View)
24 23
TER1 25
GND(LN A) 26
SW 5
GND(LN A) 27
LNAIN 28
GND 29
LNAOUT 30
E XTCAP 31
GND 32
1
2
22 21 20 19 18 17
SW 6
16 GND
SW 1
SW 4-1
SW3 SW7
SW 8
15 TX
14 GND
SW 4-2
SW 9
13 EX T1
12 GND
ANT-SW CONTROL VO LTAGE
A NT-SW
DECO RDER
SW 2
11 EX T2
10 GND
9 VDD
34
5
67
8
-1-
1 page  
NJG1707PG1
nTERMINAL INFORMATION
PIN NO. SYMBOL
DESCRIPTIONS
4 CTL1
5 CTL2
6 CTL3
7 VSS
9 VDD
11 EXT2
13 EXT1
15 TX
17 TER2
19 ANT1
21 RX
23 ANT2
25 TER1
26,27
28
30
GND(LNA)
LNAIN
LNAOUT
31 EXTCAP
1,2,3,8,10,
12,14,16,1
8,20,22,24,
29,32
GND
Control signal input terminal of high impedance C-MOS logic. Logic level: High; more
than +2V, Low; 0~+0.6V. Please connect to GND or VDD with 100kΩ if potential is
open or uncertain.
Negative supply terminal. Negative voltage of -3.5~-2.0V must be supplied on Tx
mode. This terminal is isolated on Rx mode, so open or –2.5~0V condition can be
used. Please connect bypass capacitor with GND to keep RF performance.
Positive supply terminal. The voltage of this terminal should be supplied before or
same time with other DC supplying terminals (CTL1~3, VSS). The bias voltage should
be +2.7~+5.0V. Please connect bypass capacitor with GND to keep RF performance.
RF port for Rx signal. A DC cut capacitor (56pF~100pF) is required to block VDD
voltage.
RF port for Tx/Rx signal. A DC cut capacitor (56pF~100pF) is required to block VDD
voltage.
Tx power input terminal. A DC cut capacitor is required to block VDD voltage, and also
an external matching circuit is required to improve VSWR(See Application circuit).
A termination terminal for ANT1 in case ANT2 is in use. The influence of ANT1
against ANT2 is reduced. A DC cut capacitor (10pF) is required to block VDD voltage.
RF port for Tx/Rx signal. A DC cut capacitor (56pF~100pF) is required to block VDD
voltage.
Rx output terminal. A DC cut capacitor is required to block VDD voltage, and also an
external matching circuit is required to improve VSWR(See Application circuit).
RF port for Rx signal. A DC cut capacitor (56pF~100pF) is required to block VDD
voltage.
A termination terminal for ANT2 in case ANT1 is in use. The influence of ANT2
against ANT1 is reduced. A DC cut capacitor (10pF) is required to block VDD voltage.
Ground terminal of LNA. Please place ground plane close to this pin for good RF
performance.
LNA input terminal. An external matching circuit is required.
LNA output terminal. An external matching circuit with LNA biasing element L3, L4 as
in application circuit is required.
Bypass capacitor terminal of LNA. Please place C9 as in application circuit close to
this terminal.
Ground terminal. Please connect to ground plane as close as possible for good RF
performance.
nTRUTH TABLE
”H”=VCTL (H), ”L”=VCTL (L), ”X”=H or L
CONTROL INPUT
CONTROL OUTPUT
ROUTE
Tx/Rx Diversity IN/OUT
SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 SW9
CTL1 CTL2 CTL3
Tx-ANT1
H
X
H OFF OFF OFF ON ON OFF OFF OFF ON
Tx-EXT1
H
X
L OFF OFF ON OFF ON ON ON OFF OFF
Rx-ANT1
L
L
H OFF OFF ON OFF ON OFF ON ON ON
Rx-ANT2
L
H
H ON OFF OFF OFF OFF ON ON ON ON
Rx-EXT1
L
L
L OFF OFF OFF ON ON ON OFF ON OFF
Rx-EXT2
L
H
L OFF ON OFF OFF ON ON ON ON ON
-5-
5 Page 
nTYPICAL CHARACTERISTICS (LNA)
Measured on the PCB evaluation circuit.
LNA NF,Gain vs. Frequency
(V =2.7V,I =2.7mA)
19
DD3
DD3
2
18
GAIN
17
1.8
1.6
16
NF
15
1.4
1.2
14
750
800 850 900
Frequency (MHz)
1
950
5
4.5
4
3.5
3
2.5
2
2.5
LNA I ,P-1dB vs. V
DD3
DD3
(f=820MHz)
P-1dB
I
DD3
3 3.5 4 4.5
V (V)
DD3
6
4
2
0
-2
-4
-6
5
4
2
0
-2
-4
-6
-8
-10
2.5
LNA IIP3,OIP3 vs. V
DD3
(f=820+820.1MHz,Pin=-30dBm)
OIP3
IIP3
3 3.5 4 4.5
V (V)
DD3
18
16
14
12
10
8
6
4
5
NJG1707PG1
19
18
17
16
15
14
2.5
LNA Gain,NF vs. V
DD3
(f=820MHz)
Gain
NF
3 3.5 4 4.5
V (V)
DD3
2
1.8
1.6
1.4
1.2
1
5
LNA Pout,IM3 vs. Pin
(V =2.7V,I =2.7mA,f=820+820.1MHz)
10
DD3
DD3
0
Pout
-10
-20
IM3
-30
-40
-50
-60
-70
-40 -35 -30 -25 -20 -15 -10
Input Power (dBm)
-5
0
ANT SW - LNA OUT Isolation vs. Frequency
( RX and LNAin :50ohm terminated,V =3.5V , V =0V)
-30 DD SS
RX-ANT2 Thru
-40
RX-EXT1 Thru
-50
RX-ANT1 Thru
-60
-70
RX-EXT2 Thru
-80
100 200 300 400 500 600 700 800 900 1000
Frequency (MHz)
- 11 -
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet NJG1707PG1.PDF ] | |
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