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PDF NE5537D Data sheet ( Hoja de datos )
| Número de pieza | NE5537D | |
| Descripción | Sample-and-hold amplifier | |
| Fabricantes | Philipss | |
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Philips Semiconductors Linear Products
Sample-and-hold amplifier
Product specification
NE/SE5537
DESCRIPTION
The NE5537 monolithic sample-and-hold amplifier combines the
best features of ion-implanted JFETs with bipolar devices to obtain
high accuracy, fast acquisition time, and low droop rate. This device
is pin-compatible with the LF198, and features superior performance
in droop rate and output drive capability. The circuit shown in Figure
1 contains two operational amplifiers which function as a unity gain
amplifier in the sample mode. The first amplifier has bipolar input
transistors which give the system a low offset voltage. The second
amplifier has JFET input transistors to achieve low leakage current
from the hold capacitor. A unique circuit design for leakage current
cancellation using current mirrors gives the NE5537 a low droop
rate at higher temperature. The output stage has the capability to
drive a 2kΩ load. The logic input is compatible with TTL, PMOS or
CMOS logic. The differential logic threshold is 1.4V with the sample
mode occurring when the logic input is high. It is available in 8-lead
TO-5, 8-pin plastic DIP packages, and 14-pin SO packages.
FEATURES
• Operates from ±5V to ±18V supplies
• Hold leakage current 6pA @ TJ = 25°C
• Less than 4µs acquisition time
• TTL, PMOS, CMOS compatible logic input
• 0.5mV typical hold step at CH=0.01µF
• Low input offset: 1MV (typical)
• 0.002% gain accuracy with RL=2kΩ
• Low output noise in hold mode
• Input characteristics do not change during hold mode
• High supply rejection ratio in sample or hold
• Wide bandwidth
PIN CONFIGURATIONS
FE and N Packages
V+ 1
OFFSET ADJUST 2
INPUT 3
V– 4
8 LOGIC
7 LOGIC REFERENCE
6 Ch
5 OUTPUT
D1 Package
INPUT 1
NC 2
V– 3
NC 4
NC 5
NC 6
OUTPUT 7
14 VOS ADJ
13 NC
12 V+
11 LOGIC
10 LOGIC REFERENCE
9 NC
8 Ch
NOTE:
1. SO and non-standard pinouts.
BLOCK DIAGRAM
OFFSET
2
3
INPUT
LOGIC 8
7
LOGIC
REFERENCE
–
+
–
+
30k
5
OUTPUT
300
6
HOLD
CAPACITOR
ORDERING INFORMATION
DESCRIPTION
8-Pin Plastic Dual In-Line Package (DIP)
14-Pin Plastic Small Outline (SO) Package
8-Pin Plastic Dual In-Line Package (DIP)
TEMPERATURE RANGE
0 to +70°C
0 to +70°C
-55°C to +125°C
ORDER CODE
NE5537N
NE5537D
SE5537FE
DWG #
0404B
0175D
0404B
August 31, 1994
884 853-1044 13721
1 page  
Philips Semiconductors Linear Products
Sample-and-hold amplifier
Product specification
NE/SE5537
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Dynamic Sampling Error
100
330pF
10 0.01µF
0.033µF
0.1µF
0.03µF
±1 3300pF
–10
1000pF
–100
0.1
1 10 100
INPUT SLEW RATE (V/ms)
1000
Output Droop Rate
100
10–1
10–2
TJ = 85°C
10–3 TJ = 25°C
10–4
100pF 1000pF
0.01µF
0.1µF
HOLD CAPACITOR
1µF
Hold Settling Time
2
1.8 V+ = V– = 15V
1.6 SETTLING TO 1mV
1.4
1.2
1
0.8
0.6
0.4
0.2
0
–50 –25 0 25 50 75 100 125 150
JUNCTION TEMPERATURE (°C)
Phase and Gain
(Input-to-Output, Small-Signal)
5
0
–5
–10
1k
10k 100k 1M
FREQUENCY (Hz)
80
70
60
50
40
30
20
10
0
10M
Power Supply Rejection
160
140
TJ = 25°C
V+ = V– = 15V
VOUT = 0V
120
100
80
NEGATIVE
60 SUPPLY
POSITIVE
SUPPLY
40
20
0
100
1k 10k 100k
FREQUENCY (Hz)
1M
Output Noise
160
140
120
100
“HOLD” MODE
80
60
40
20 SAMPLE MODE
0
10
100 1k 10k
FREQUENCY (Hz)
100k
August 31, 1994
–130
–120
–110
–100
–90
–80
–70
–60
–50
1
Feedthrough Rejection
Ratio (Hold Mode)
Ch = 0.1µF
V+ = V– = 15V
VIN = 10VP-P
V7,8 = 0
TJ = 25°C
Ch = 0.01µF
Ch = 1000pF
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
888
5 Page | ||
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| PDF Descargar | [ Datasheet NE5537D.PDF ] | |
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