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PDF 82C55 Data sheet ( Hoja de datos )
| Número de pieza | 82C55 | |
| Descripción | CMOS PROGRAMMABLE PERIPHERAL INTERFACE | |
| Fabricantes | OKI electronic componets | |
| Logotipo |  |
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E2O0020-27-X3
¡ Semiconductor¡ Semiconductor
MSTMh8is2Cve5r5sAio-n2:RJSa/nG. 1S9/9V8JS
Previous version: Aug. 1996
MSM82C55A-2RS/GS/VJS
CMOS PROGRAMMABLE PERIPHERAL INTERFACE
GENERAL DESCRIPTION
The MSM82C55A-2 is a programmable universal I/O interface device which operates as high
speed and on low power consumption due to 3m silicon gate CMOS technology. It is the best
fit as an I/O port in a system which employs the 8-bit parallel processing MSM80C85AH CPU.
This device has 24-bit I/O pins equivalent to three 8-bit I/O ports and all inputs/outputs are
TTL interface compatible.
FEATURES
• High speed and low power consumption due to 3m silicon gate CMOS technology
• 3 V to 6 V single power supply
• Full static operation
• Programmable 24-bit I/O ports
• Bidirectional bus operation (Port A)
• Bit set/reset function (Port C)
• TTL compatible
• Compatible with 8255A-5
• 40-pin Plastic DIP (DIP40-P-600-2.54): (Product name: MSM82C55A-2RS)
• 44-pin Plastic QFJ (QFJ44-P-S650-1.27): (Product name: MSM82C55A-2VJS)
• 44-pin Plastic QFP (QFP44-P-910-0.80-2K): (Product name: MSM82C55A-2GS-2K)
1/26
1 page  
¡ Semiconductor
MSM82C55A-2RS/GS/VJS
AC CHARACTERISTICS
Parameter
Setup Time of Address to the Falling Edge of RD
Hold Time of Address to the Rising Edge of RD
RD Pulse Width
Delay Time from the Falling Edge of RD to the Output of
Defined Data
Delay Time from the Rising Edge of RD to the Floating of
Data Bus
Time from the Rising Edge of RD or WR to the Next Falling
Edge of RD or WR
Setup Time of Address before the Falling Edge of WR
Hold Time of Address after the Rising Edge of WR
WR Pulse Width
Setup Time of Bus Data before the Rising Edge of WR
Hold Time of Bus Data after the Rising Edge of WR
Delay Time from the rising Edge of WR to the Output of
Defined Data
Setup Time of Port Data before the Falling Edge of RD
Hold Time of Port Data after the Rising Edge of RD
ACK Pulse Width
STB Pulse Width
Setup Time of Port Data before the rising Edge of STB
Hold Time of Port Bus Data after the rising Edge of STB
Delay Time from the Falling Edge of ACK to the Output of
Defined Data
Delay Time from the Rising Edge of ACK to the Floating of
Port (Port A in Mode 2)
Delay Time from the Rising Edge of WR to the Falling Edge of
OBF
Delay Time from the Falling Edge of ACK to the Rising Edge of
OBF
Delay Time from the Falling Edge of STB to the Rising Edge of
IBF
Delay Time from the Rising Edge of RD to the Falling Edge of
IBF
Delay Time from the the Falling Edge of RD to the Falling Edge
of INTR
Delay Time from the Rising Edge of STB to the Rising Edge of
INTR
Delay Time from the Rising Edge of ACK to the Rising Edge of
INTR
Delay Time from the Falling Edge of WR to the Falling Edge of
INTR
(VCC = 4.5 V to 5.5 V, Ta = –40 to +85°C)
MSM82C55A-2
Symbol
Unit
Remarks
Min. Max.
tAR 20 — ns
tRA 0 — ns
tRR 100 — ns
tRD — 120 ns
tDF 10 75 ns
tRV 200 — ns
tAW 0 — ns
tWA 20 — ns
tWW 150 — ns
tDW 50 — ns
tWD 30 — ns
tWB — 200 ns
tIR 20 — ns
tHR 10 — ns
tAK 100 — ns Load
tST 100 — ns 150 pF
tPS 20 — ns
tPH 50 — ns
tAD — 150 ns
tKD 20 250 ns
tWOB — 150 ns
tAOB — 150 ns
tSIB — 150 ns
tRIB — 150 ns
tRIT — 200 ns
tSIT — 150 ns
tAIT — 150 ns
tWIT — 250 ns
Note: Timing measured at VL = 0.8 V and VH = 2.2 V for both inputs and outputs.
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5 Page 
¡ Semiconductor
MSM82C55A-2RS/GS/VJS
OPERATIONAL DESCRIPTION
Control Logic
Operations by addresses and control signals, e.g., read and write, etc. are as shown in the table
below:
Operaiton
A1 A0 CS WR RD
Operation
0 0 0 10
Port A Æ Data Bus
Input
010
10
Port B Æ Data Bus
1 0 0 10
Port C Æ Data Bus
000
01
Data Bus Æ Port A
Output
010
01
Data Bus Æ Port B
1 0 0 0 1 Data Bus Æ Port C
Control
110
01
Data Bus Æ Control Register
Others
110
¥¥1
10
¥¥
Illegal Condition
Data bus is in the high impedance status.
Setting of Control Word
The control register is composed of 7-bit latch circuit and 1-bit flag as shown below.
Group A Control Bits
Group B Control Bits
D7 D6 D5 D4 D3 D2 D1 D0
Control word Identification flag
Be sure to set 1 for the control word
to define a mode and input/output.
When set to 0, it becomes
the control word for bit set/
reset.
Definition of input/
output of low order
4 bits of port C.
Definition of input/
output of 8 bits of
port B.
Mode definition of
group B.
0 = Output
1 = Input
0 = Output
1 = Input
0 = Mode 0
1 = Mode 1
Definition of input/
output of high order
4 bits of port C.
Definition of input/
output of 8 bits of
port A.
0 = Output
1 = Input
0 = Output
1 = Input
Mode definition of group A.
D6 D5
00
01
1¥
Mode
Mode 0
Mode 1
Mode 2
11/26
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| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet 82C55.PDF ] | |
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