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82434LX Datasheet دیتاشیت PDF دانلود

دیتاشیت - Intel Corporation - PCI/ CACHE AND MEMORY CONTROLLER PCMC

شماره قطعه 82434LX
شرح مفصل PCI/ CACHE AND MEMORY CONTROLLER PCMC
تولید کننده Intel Corporation 
آرم Intel Corporation 


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82434LX شرح
82434LX 82434NX PCI CACHE AND MEMORY
CONTROLLER (PCMC)
Y Supports the PentiumTM Processor at
iCOMPTM Index 510T60 MHz and iCOMP
Index 567T66 MHz
Y Supports the Pentium Processor at
iCOMP Index 735T90 MHz iCOMP Index
815T100 MHz and iCOMP Index 610T75
MHz
Y Supports Pipelined Addressing
Capability of the Pentium Processor
Y The 82430NX Drives 3 3V Signal Levels
on the CPU and Cache Interfaces
Y High Performance CPU PCI Memory
Interfaces via Posted Write and Read
Prefetch Buffers
Y Fully Synchronous PCI Interface with
Full Bus Master Capability
Y Supports the Pentium Processor
Internal Cache in Either Write-Through
or Write-Back Mode
Y Programmable Attribute Map of DOS
and BIOS Regions for System
Flexibility
Y Integrated Low Skew Clock Driver for
Distributing Host Clock
Y Integrated Second Level Cache
Controller
Integrated Cache Tag RAM
Write-Through and Write-Back Cache
Modes for the 82434LX
Write-Back for the 82434NX
82434NX Supports Low-Power Cache
Standby
Direct Mapped Organization
Supports Standard and Burst SRAMs
256-KByte and 512-KByte Sizes
Cache Hit Cycle of 3-1-1-1 on Reads
and Writes Using Burst SRAMs
Cache Hit Cycle of 3-2-2-2 on Reads
and 4-2-2-2 on Writes Using
Standard SRAMs
Y Integrated DRAM Controller
Supports 2 MBytes to 192 MBytes of
Cacheable Main Memory for the
82434LX
Supports 2 MBytes to 512 MBytes of
Cacheable Main Memory for the
82434NX
Supports DRAM Access Times of
70 ns and 60 ns
CPU Writes Posted to DRAM 4-1-1-1
Refresh Cycles Decoupled from ISA
Refresh to Reduce the DRAM
Access Latency
Six RAS Lines (82434LX)
Eight RAS Lines (82434NX)
Refresh by RAS -Only or CAS-
Before-RAS in Single or Burst
of Four
Y Host PCI Bridge
Translates CPU Cycles into PCI Bus
Cycles
Translates Back-to-Back Sequential
CPU Memory Writes into PCI Burst
Cycles
Burst Mode Writes to PCI in Zero PCI
Wait-States (i e Data Transfer Every
Cycle)
Full Concurrency Between CPU-to-
Main Memory and PCI-to-PCI
Transactions
Full Concurrency Between CPU-to-
Second Level Cache and PCI-to-Main
Memory Transactions
Same Cache and Memory System
Logic Design for ISA and EISA
Systems
Cache Snoop Filter Ensures Data
Consistency for PCI-to-Main Memory
Transactions
Y 208-Pin QFP Package
Other brands and names are the property of their respective owners
December 1994
Order Number 290479-004

قانون اساسیصفحه 30
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