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PDF MAX1426 Data sheet ( Hoja de datos )
| Número de pieza | MAX1426 | |
| Descripción | 10-Bit / 10Msps ADC | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-1598 Rev 0; 1/00
10-Bit, 10Msps ADC
General Description
The MAX1426 10-bit, monolithic analog-to-digital con-
verter (ADC) is capable of a 10Msps sampling rate. This
device features an internal track-and-hold (T/H) amplifier
for excellent dynamic performance; at the same time, it
minimizes the number of external components. Low
input capacitance of only 8pF minimizes input drive
requirements. A wide input bandwidth (up to 150MHz)
makes this device suitable for digital RF/IF downconvert-
er applications employing undersampling techniques.
The MAX1426 employs a differential pipelined architec-
ture with a wideband T/H amplifier to maximize through-
put while limiting power consumption to only 156mW.
The MAX1426 generates an internal +2.5V reference
that supplies three additional reference voltages
(+3.25V, +2.25V, and +1.25V). These reference volt-
ages provide a differential input range of +2V to -2V.
The analog inputs are biased internally to correct the
DC level, eliminating the need for external biasing on
AC-coupled applications.
A separate +3V digital logic supply input allows for
separation of digital and analog circuitry. The output
data is in two’s complement format. The MAX1426 is
available in the space-saving 28-pin SSOP package.
For a pin-compatible version at a higher data rate, refer
to the MAX1424 or MAX1425
Applications
Medical Ultrasound Imaging
CCD Pixel Processing
IR Focal Plane Array
Radar
IF and Baseband Digitization
Set-Top Boxes
Functional Diagram
CLK
INP
T/H
INN
REF
INTERFACE
PIPELINE ADC
REF SYSTEM +
BIAS
MAX1426
OUTPUT
DRIVERS
AVDD
AGND
D9–D0
DVDD
DGND
REFIN REFP CML REFN
OE/PD
Features
o Differential Inputs for High Common-Mode
Noise Rejection
o 61dB Signal-to-Noise Ratio (at fIN = 2MHz)
o Internal +2.5V Reference
o 150MHz Input Bandwidth
o Wide ±2V Input Range
o Low Power Consumption: 156mW
o Separate Digital Supply Input for 3V Logic
Compatibility
o Single +5V Operation Possible
PART
MAX1426CAI
MAX1426EAI
Ordering Information
TEMP. RANGE
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
28 SSOP
28 SSOP
Pin Configuration
TOP VIEW
AGND 1
AVDD 2
REFP 3
REFIN 4
REFN 5
CML 6
AGND 7
AVDD 8
INP 9
INN 10
CMLP 11
CMLN 12
CLK 13
OE/PD 14
MAX1426
SSOP
28 D0
27 D1
26 D2
25 D3
24 D4
23 DGND
22 DVDD
21 DGND
20 DVDD
19 D5
18 D6
17 D7
16 D8
15 D9
________________________________________________________________ Maxim Integrated Products 1
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
1 page  
10-Bit, 10Msps ADC
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = VDGND = 0, internal reference, digital output loading 35pF, fCLK =
10MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
TIMING CHARACTERISTICS
Conversion Rate
Clock Frequency
Clock High
Clock Low
Pipeline Delay (Latency)
Aperture Delay
Aperture Jitter
Data Output Delay
Bus Enable
Bus Disable
SYMBOL
CONV
fCLK
tCH
tCL
Figure 4
Figure 4
tAD
tAJ
tOD
CONDITIONS
MIN TYP MAX UNITS
0.1
40 50
40 50
5.5
5
7
5 20
10
10
10 MHz
10 MHz
60 ns
60 ns
cycles
ns
ps
25 ns
20 ns
20 ns
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Internal reference, REFIN bypassed to AGND with a 0.1µF capacitor.
External +2.5V reference applied to REFIN.
Internal reference disabled. VREFIN = 0, VREFP = 3.25V, VCML = 2.25V, and VREFN = 1.25V.
Measured as the ratio of the change in midscale offset voltage for a ±5% change in VAVDD using the internal reference.
IMD is measured with respect to either of the fundamental tones.
Specifies the common-mode range of the differential input signal supplied to the MAX1426.
Defined as the input frequency at which the fundamental component of the output spectrum is attenuated by 3dB.
VREFIN is internally biased to +2.5V through a 5kΩ resistor.
_______________________________________________________________________________________ 5
5 Page 
10-Bit, 10Msps ADC
ANALOG INPUT
5.5 CLOCK-CYCLE LATENCY
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
CLOCK INPUT
DATA OUTPUT
n-6 n-5 n-4 n-3 n-2 n-1 n n+1
Figure 3. System Timing Diagram
INPUT
CLK
tOD
tCLK
tCH
tCI
OUTPUT
DATA
DATA 0
DATA 1
DATA 2
Figure 4. Output Timing Diagram
and REFN. In this mode, the voltages at these pins
are set to their nominal values (see Electrical
Characteristics). The reference voltage levels can be
adjusted externally by applying a voltage at REFIN.
This allows other input levels to be used as well. The
full external reference mode is entered when REFIN =
AGND. External voltages can be applied to REFP,
CML, and REFIN. In this mode, the internal voltage
shuts down, resulting in less overall power consump-
tion.
Clock Input (CLK)
CLK is TTL/CMOS compatible. Since the interstage
conversion of the device depends on the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (<2ns). Low clock jitter
improves SNR performance. The MAX1426 operates
with a 50% duty cycle. If the clock has a duty cycle
other than 50%, the clock must meet the specifications
for high and low periods as stated in the Electrical
Characteristics.
Table 1. MAX1426 Output Code
DIFFERENTIAL INPUT
OUTPUT CODE
(TWO’S COMPLEMENT)
+Full Scale
0111111111
+Full Scale 1LSB
0111111110
+Full Scale 2LSB
0111111101
+3/4 Full Scale
0110000000
+1/2 Full Scale
0100000000
+1/4 Full Scale
0010000000
+1 LSB
0000000001
Bipolar Zero
0000000000
-1 LSB
1111111111
-1/4 Full Scale
1110000000
-1/2 Full Scale
1100000000
-3/4 Full Scale
1010000000
-Full Scale + 1LSB
1000000001
-Full Scale
1000000000
Output Enable/Power-Down Function
(OE/PD) and Output Data
All data outputs, D0 through D9, are TTL/CMOS-logic
compatible. There is a 5.5 clock-cycle latency between
the start convert signal and the valid output data. The
output coding for the MAX1426 is in binary two’s com-
plement format, which has the MSB inverted (Table 1).
The digital output goes into a high-impedance state
and the device into a low-power mode when OE/PD
goes high. For normal operation, drive OE low. The out-
puts are not designed to drive high capacitances or
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MAX1426.PDF ] | |
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