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7C256 fiches techniques PDF

ETC - High Performance 32Kx8 CMOS SRAM

Numéro de référence 7C256
Description High Performance 32Kx8 CMOS SRAM
Fabricant ETC 
Logo ETC 





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7C256 fiche technique
High Performance
32K×8
CMOS SRAM
32K×8 CMOS SRAM (Common I/O)
AS7C256
AS7C256L
FEATURES
• Organization: 32,768 words × 8 bits
• High speed
– 10/12/15/20/25/35 ns address access time
– 3/3/4/5/6/8 ns output enable access time
• Low power consumption
– Active: 660 mW max (10 ns cycle)
– Standby: 11 mW max, CMOS I/O
2.75 mW max, CMOS I/O, L version
– Very low DC component in active power
• 2.0V data retention (L version)
• Equal access and cycle times
• Easy memory expansion with CE and OE inputs
• TTL-compatible, three-state I/O
• 28-pin JEDEC standard packages
– 300 mil PDIP and SOJ
Socket compatible with 7C512 and 7C1024
– 330 mil SOIC
– 8×13.4 TSOP
• ESD protection > 2000 volts
• Latch-up current > 200 mA
LOGIC BLOCK DIAGRAM
PIN ARRANGEMENT
Vcc
GND
A0
A1
A2
A3
A4
A5
A6
A14
INPUT BUFFER
256×128×8
ARRAY
(262,144)
I/O7
I/O0
COLUMN DECODER
AAAAAAA
7 8 9 10 11 12 13
CONTROL
CIRCUIT
WE
OE
CE
SELECTION GUIDE
AS7C256-01
DIP, SOJ, SOIC
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
TSOP 8×13.4
OE
A11
A9
A8
A13
WE
Vcc
A14
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
1 28 Vcc
2 27 WE
3 26 A13
4 25 A8
5 24 A9
6 23 A11
7 22 OE
8 21 A10
9 20 CE
10 19 I/O7
11 18 I/O6
12 17 I/O5
13 16 I/O4
14 15 I/O3
AS7C256
21 A10
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
14 GND
13 I/O2
12 I/O1
11 I/O0
10 A0 AS7C256-02
9 A1
8 A2
Maximum Address Access Time
Maximum Output Enable Access Time
Maximum Operating Current
Maximum CMOS Standby Current
L
7C256-10 7C256-12 7C256-15 7C256-20 7C256-25 7C256-35 Unit
10 12 15 20 25 35 ns
3 3 4 5 6 8 ns
120 115 110 100 90 80 mA
2.0 2.0 2.0 2.0 2.0 2.0 mA
0.5 0.5 0.5 0.5 0.5 0.5 mA
ALLIANCE SEMICONDUCTOR

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