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PDF MAX1185 Data sheet ( Hoja de datos )
| Número de pieza | MAX1185 | |
| Descripción | Low-Power ADC | |
| Fabricantes | Maxim Integrated | |
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19-2175; Rev 3; 5/11
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
General Description
The MAX1185 is a 3V, dual 10-bit analog-to-digital con-
verter (ADC) featuring fully-differential wideband track-
and-hold (T/H) inputs, driving two pipelined, nine-stage
ADCs. The MAX1185 is optimized for low-power, high
dynamic performance applications in imaging, instru-
mentation, and digital communication applications. This
ADC operates from a single 2.7V to 3.6V supply, con-
suming only 105mW while delivering a typical signal-to-
noise ratio (SNR) of 59.5dB at an input frequency of
7.5MHz and a sampling rate of 20Msps. Digital outputs
A and B are updated alternating on the rising (CHA)
and falling (CHB) edge of the clock. The T/H driven
input stages incorporate 400MHz (-3dB) input ampli-
fiers. The converters may also be operated with single-
ended inputs. In addition to low operating power, the
MAX1185 features a 2.8mA sleep mode as well as a
1µA power-down mode to conserve power during idle
periods.
An internal 2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure allows the use of this internal or an externally
derived reference, if desired for applications requiring
increased accuracy or a different input voltage range.
The MAX1185 features parallel, multiplexed, CMOS-
compatible three-state outputs. The digital output for-
mat can be set to two’s complement or straight offset
binary through a single control pin. The device provides
for a separate output power supply of 1.7V to 3.6V for
flexible interfacing. The MAX1185 is available in a 7mm
x 7mm, 48-pin TQFP package, and is specified for the
extended industrial (-40°C to +85°C) temperature
range.
Pin-compatible, nonmultiplexed. high-speed versions of
the MAX1185 are also available. Refer to the MAX1180
data sheet for 105Msps, the MAX1181 data sheet for
80Msps, the MAX1182 data sheet for 65Msps, the
MAX1183 data sheet for 40Msps, and the MAX1184
data sheet for 20Msps.
High Resolution Imaging
I/Q Channel Digitization
Multichannel IF Sampling
Instrumentation
Video Application
Ultrasound
Applications
Features
o Single 3V Operation
o Excellent Dynamic Performance:
59.5dB SNR at fIN = 7.5MHz
74dB SFDR at fIN = 7.5MHz
o Low Power:
35mA (Normal Operation)
2.8mA (Sleep Mode)
1µA (Shutdown Mode)
o 0.02dB Gain and 0.25° Phase Matching
o Wide ±1Vp-p Differential Analog Input Voltage
Range
o 400MHz, -3dB Input Bandwidth
o On-Chip 2.048V Precision Bandgap Reference
o Single 10-Bit Bus for Multiplexed, Digital Outputs
o User-Selectable Output Format—Two’s
Complement or Offset Binary
o 48-Pin TQFP Package with Exposed Pad for
Improved Thermal Dissipation
Ordering Information
PART
TEMP
RANGE
PIN-PACKAGE
MAX1185ECM
-40°C to +85°C 48 TQFP-EP*
MAX1185ECM+
-40°C to +85°C 48 TQFP-EP*
MAX1185ECM/V+ -40°C to +85°C 48 TQFP-EP*
*EP = Exposed pad.
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
Pin-Compatible Versions table at end of data sheet.
Pin Configuration
COM 1
VDD 2
GND 3
INA+ 4
INA- 5
VDD 6
GND 7
INB- 8
INB+ 9
GND 10
VDD 11
CLK 12
MAX1185
EP
36 D1A/B
35 D0A/B
34 OGND
33 OVDD
32 OVDD
31 OGND
30 A/B
29 N.C.
28 N.C.
27 N.C.
26 N.C.
25 N.C.
48 TQFP-EP
NOTE: THE PIN 1 INDICATOR FOR LEAD-FREE
PACKAGES IS REPLACED BY A "+" SIGN.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 1), fCLK = 20MHz, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
Analog Supply Current
Output Supply Current
Power Dissipation
Power-Supply Rejection Ratio
TIMING CHARACTERISTICS
CLK Rise to CHA Output Data
Valid
CLK Fall to CHB Output Data
Valid
VDD
OVDD
IVDD
IOVDD
PDISS
PSRR
Operating, fINA or B = 7.5MHz at -0.5dBFS
Sleep mode
Shutdown, clock idle, PD = OE = OVDD
Operating, CL = 15pF,
fINA or B = 7.5MHz at -0.5dBFS
Sleep mode
Shutdown, clock idle, PD = OE = OVDD
Operating, fINA or B = 7.5MHz at -0.5dBFS
Sleep mode
Shutdown, clock idle, PD = OE = OVDD
Offset
Gain
tDOA Figure 3 (Note 5)
tDOB Figure 3 (Note 5)
2.7 3.0 3.6
V
1.7 2.5 3.6
V
35 50
mA
2.8
1 15 µA
9 mA
100
2 10
µA
105 150
mW
8.4
3 45 µW
±0.2 mV/V
±0.1 %/V
5 8 ns
5 8 ns
Clock Rise/Fall to A/B Rise/Fall
Time
tDA/B
6 ns
Output Enable Time
Output Disable Time
CLK Pulse Width High
CLK Pulse Width Low
Wake-Up Time
tENABLE
tDISABLE
tCH
tCL
tWAKE
Figure 4
Figure 4
Figure 3, clock period: 50ns
Figure 3, clock period: 50ns
Wake-up from sleep mode (Note 6)
Wake-up from shutdown (Note 6)
10
1.5
25 ± 7.5
25 ± 7.5
0.51
1.5
ns
ns
ns
ns
µs
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
Gain Matching
Phase Matching
fINA or B = 7.5MHz at -0.5dBFS
fINA or B = 7.5MHz at -0.5dBFS
fINA or B = 7.5MHz at -0.5dBFS
-70 dB
0.02 ±0.2
dB
0.25 Degrees
Note 1: Equivalent dynamic performance is obtainable over full OVDD range with reduced CL.
Note 2: Specifications at ≥ +25°C are guaranteed by production test and < +25°C are guaranteed by design and characterization.
Note 3: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a ±1.024V full-scale
input voltage range.
Note 4: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB or better, if referenced to the two-tone envelope.
Note 5: Digital outputs settle to VIH, VIL. Parameter guaranteed by design.
Note 6: With REFIN driven externally, REFP, COM, and REFN are left unconnected while powered down.
_______________________________________________________________________________________ 5
5 Page 
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
VIN T/H Σ x2 VOUT
VIN T/H Σ x2 VOUT
FLASH
ADC
DAC
1.5 BITS
STAGE 1
STAGE 2
STAGE 8
2-BIT FLASH
ADC
STAGE 9
FLASH
ADC
DAC
1.5 BITS
STAGE 1
STAGE 2
STAGE 8
2-BIT FLASH
ADC
STAGE 9
T/H
VINA
DIGITAL CORRECTION LOGIC
10
Figure 1. Pipelined Architecture—Stage Blocks
T/H
VINB
OUTPUT
MULTIPLEXER
10
D0A/B–D9A/B
DIGITAL CORRECTION LOGIC
10
INTERNAL BIAS
COM
S2a S5a
C1a S3a
S4a
INA+
C2a
S4c S1
OUT
INA-
S4b
S4a
C2b
S2b
INTERNAL BIAS
INTERNAL BIAS
S2a
OUT
C1b S3b
S5b
COM
COM
S5a
C1a S3a
HOLD
HOLD
CLK
TRACK
TRACK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
INB+
C2a
S4c S1
OUT
MAX1185
INB-
S4b
C2b
S2b
INTERNAL BIAS
OUT
C1b S3b
S5b
COM
Figure 2. MAX1185 T/H Amplifiers
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet MAX1185.PDF ] | |
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