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PDF MAX1168 Data sheet ( Hoja de datos )
| Número de pieza | MAX1168 | |
| Descripción | Multichannel / 16-Bit / 200ksps Analog-to-Digital Converters | |
| Fabricantes | Maxim Integrated | |
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19-2956; Rev 0; 8/03
EVAALVUAAILTAIOBNLEKIT
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
General Description
The MAX1167/MAX1168 low-power, multichannel, 16-
bit analog-to-digital converters (ADCs) feature a suc-
cessive-approximation ADC, integrated +4.096V
reference, a reference buffer, an internal oscillator,
automatic power-down, and a high-speed SPI™/
QSPI™/MICROWIRE™-compatible interface. The
MAX1167/MAX1168 operate with a single +5V analog
supply and feature a separate digital supply, allowing
direct interfacing with +2.7V to +5.5V digital logic.
The MAX1167/MAX1168 consume only 2.9mA (AVDD =
DVDD = +5V) at 200ksps when using an external reference.
AutoShutdown™ reduces the supply current to 145µA at
10ksps and to less than 10µA at reduced sampling rates.
The MAX1167 includes a 4-channel input multiplexer, and
the MAX1168 accepts up to eight analog inputs.
In addition, digital signal processor (DSP)-initiated con-
versions are simplified with the DSP frame-sync input and
output featured in the MAX1168. The MAX1168 includes
a data-bit transfer input to select between 8-bit-wide or
16-bit-wide data-transfer modes. Both devices feature a
scan mode that converts each channel sequentially or
one channel continuously.
Excellent dynamic performance and low power, com-
bined with ease of use and an integrated reference, make
the MAX1167/MAX1168 ideal for control and data-acqui-
sition operations or for other applications with demanding
power consumption and space requirements. The
MAX1167 is available in a 16-pin QSOP package and the
MAX1168 is available in a 24-pin QSOP package. Both
devices are guaranteed over the commercial (0°C to
+70°C) and extended (-40°C to +85°C) temperature
ranges. Use the MAX1168 evaluation kit to evaluate the
MAX1168.
Applications
Motor Control
Industrial Process Control
Industrial I/O Modules
Data-Acquisition Systems
Thermocouple Measurements
Accelerometer Measurements
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
Features
o 16-Bit Resolution, ±1 LSB DNL (max)
o +5V Single-Supply Operation
o Adjustable Logic Level (+2.7V to +5.25V)
o Input Voltage Range: 0 to VREF
o Internal (+4.096V) or External (+3.8V to AVDD)
Reference
o Internal Track/Hold, 4MHz Input Bandwidth
o Internal or External Clock
o SPI/QSPI/MICROWIRE-Compatible Serial
Interface, MAX1168 Performs DSP-Initiated
Conversions
o 8-Bit-Wide or 16-Bit-Wide Data-Transfer Mode
(MAX1168 Only)
o 4-Channel (MAX1167) or 8-Channel (MAX1168)
Input Mux
Scan Mode Sequentially Converts Multiple
Channels or One Channel Continuously
o Low Power
2.9mA at 200ksps
1.45mA at 100ksps
145µA at 10ksps
0.6µA in Full Power-Down Mode
o Small Package Size
16-Pin QSOP (MAX1167)
24-Pin QSOP (MAX1168)
Ordering Information
PART
TEMP RANGE
PIN-
PACKAGE
MAX1167ACEE
0°C to +70°C 16 QSOP
MAX1167BCEE
0°C to +70°C 16 QSOP
MAX1167CCEE
0°C to +70°C 16 QSOP
MAX1167AEEE* -40°C to +85°C 16 QSOP
MAX1167BEEE*
MAX1167CEEE*
-40°C to +85°C
-40°C to +85°C
16 QSOP
16 QSOP
*Future product—contact factory for availability.
INL
(LSB)
±1.2
±2
±3
±1.2
±2
±3
Ordering Information continued at end of data sheet.
Pin Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF
= +4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Shutdown Supply Current
IAVDD + CS = DVDD, SCLK = 0, DIN = 0,
IDVDD DSPR = DVDD, full power-down
0.6 10
µA
Power-Supply Rejection Ratio
PSRR
AVDD = DVDD = 4.75V to 5.25V, full-scale
input (Note 9)
63
dB
TIMING CHARACTERISTICS (Figures 1, 2, 8, and 16)
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external
VREF = +4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Acquisition Time
tACQ External clock (Note 6)
729
ns
SCLK to DOUT Valid
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS Pulse Width
tDO
tDV
tTR
tCSW
CDOUT = 30pF
CDOUT = 30pF
CDOUT = 30pF
50 ns
80 ns
80 ns
100 ns
CS to SCLK Setup
tCSS
SCLK rise
SCLK fall (DSP)
100 ns
CS to SCLK Hold
tCSH
SCLK rise
SCLK fall (DSP)
0 ns
SCLK High Pulse Width
Conversion
tCH Duty cycle 45% to 55% Data transfer
93
50
ns
SCLK Low Pulse Width
Conversion
tCL Duty cycle 45% to 55% Data transfer
93
50
ns
SCLK Period
tCP
209 ns
DIN to SCLK Setup
SCLK rise
tDS SCLK fall (DSP)
50 ns
DIN to SCLK Hold
SCLK rise
tDH SCLK fall (DSP)
0 ns
CS Falling to DSPR Rising
DSPR to SCLK Falling Setup
tDF
tFSS
100 ns
100 ns
DSPR to SCLK Falling Hold
tFSH
0 ns
_______________________________________________________________________________________ 5
5 Page 
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
PIN
MAX1167 MAX1168
— 13
— 14
— 23
— 24
Pin Description (continued)
NAME
FUNCTION
AIN6
AIN7
DSPX
N.C.
Analog Input 6
Analog Input 7
DSP Frame-Sync Transmit Output. A frame-sync pulse at DSPX notifies the DSP that the
MSB data is available at DOUT. Leave DSPX unconnected when not in DSP mode.
No Connection. Not internally connected.
DVDD
DOUT
1mA
DOUT
1mA CLOAD = 30pF
CLOAD = 30pF
DGND
a) VOL TO VOH
DGND
b) HIGH-Z TO VOL AND VOH TO VOL
Figure 1. Load Circuits for DOUT Enable Time and SCLK-to-
DOUT Delay Time
DVDD
DOUT
1mA
DOUT
1mA CLOAD = 30pF
DGND
a) VOH TO HIGH-Z
CLOAD = 30pF
DGND
b) VOL TO HIGH-Z
Figure 2. Load Circuits for DOUT Disable Time
Detailed Description
The MAX1167/MAX1168 low-power, multichannel, 16-bit
ADCs feature a successive-approximation ADC, auto-
matic power-down, integrated +4.096V reference, and a
high-speed SPI/QSPI/MICROWIRE-compatible interface.
A DSPR input and DSPX output allow the MAX1168 to
communicate with digital signal processors (DSPs) with
no external glue logic. The MAX1167/MAX1168 operate
with a single +5V analog supply and feature a separate
digital supply, allowing direct interfacing with +2.7V to
+5.5V digital logic.
Figures 3 and 4 show the functional diagrams of the
MAX1167/MAX1168, and Figures 5 and 6 show the
MAX1167/MAX1168 in a typical operating circuit. The
serial interface simplifies communication with micro-
processors (µPs).
In external reference mode, the MAX1167/MAX1168
have two power modes: normal mode and shutdown
mode. Driving CS high places the MAX1167/MAX1168 in
shutdown mode, reducing the supply current to 0.6µA
(typ). Pull CS low to place the MAX1167/MAX1168 in
normal operating mode. The internal reference mode
offers software-programmable, power-down options as
shown in Table 5.
In SPI/QSPI/MICROWIRE mode, a falling edge on CS
wakes the analog circuitry and allows SCLK to clock in
data. Acquisition and conversion are initiated by SCLK.
The conversion result is available at DOUT in unipolar
serial format. DOUT is held low until data becomes
available (MSB first) on the 8th falling edge of SCLK
when in 8-bit transfer mode, and on the 16th falling
edge when in 16-bit transfer mode (see the Operating
Modes section). Figure 8 shows the detailed SPI/QSPI/
MICROWIRE serial-interface timing diagram.
In external clock mode, the MAX1168 also interfaces
with DSPs. In DSP mode, a frame-sync pulse from the
DSP initiates a conversion that is driven by SCLK. The
MAX1168 formats a frame-sync pulse to notify the DSP
that the conversion results are available at DOUT in
MSB-first, unipolar, serial-data format. Figure 16 shows
the detailed DSP serial-interface timing diagram (see the
Operating Modes section).
Analog Input
Figure 7 illustrates the input-sampling architecture of
the ADC. The voltage applied at REF or the internal
+4.096V reference sets the full-scale input voltage.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MAX1168.PDF ] | |
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