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PDF MAX1161 Data sheet ( Hoja de datos )
| Número de pieza | MAX1161 | |
| Descripción | 10-Bit / 40Msps / TTL-Output ADC | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAX1161 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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19-1190; Rev 0; 3/97
EVAALVUAAILTAIOBNLEKIT
10-Bit, 40Msps, TTL-Output ADC
_______________General Description
The MAX1161 10-bit, monolithic analog-to-digital con-
verter (ADC) is capable of 40Msps minimum word
rates. An on-board track/hold ensures excellent dynam-
ic performance without the need for external compo-
nents. A 5pF input capacitance minimizes drive
requirement problems.
Inputs and outputs are TTL compatible. An overrange
output is provided to indicate overflow conditions.
Output data format is straight binary. Power dissipation
is low at only 1W with +5V and -5.2V power-supply volt-
ages. The MAX1161 also accepts wide, ±2V input volt-
ages.
The MAX1161 is available in 28-pin DIP and SO pack-
ages in the commercial temperature range.
________________________Applications
Medical Imaging
Professional Video
Radar Receivers
Instrumentation
Digital Communications
____________________________Features
o Monolithic 40Msps Converter
o On-Chip Track/Hold
o Bipolar, ±2V Analog Input
o 57dB SNR at 3.58MHz Input
o 5pF Input Capacitance
o TTL Outputs
______________Ordering Information
PART
MAX1161ACPI
MAX1161BCPI
MAX1161ACWI
MAX1161BCWI
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
28 Wide Plastic DIP
28 Wide Plastic DIP
28 SO
28 SO
________________Functional Diagram
ANALOG
INPUT
COARSE
ADC
4
ANALOG
PRESCALER
T/H
AMPLIFIER
BANK
SUCCESSIVE INTERPOLATION
STAGE i
SUCCESSIVE INTERPOLATION
STAGE i + 1
....
DIGITAL
OUTPUT
10
SUCCESSIVE INTERPOLATION
STAGE N
__________________Pin Configuration
TOP VIEW
DGND 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
D8 10
D9 11
D10 12
DGND 13
DVCC 14
MAX1161
DIP/SO
28 DVCC
27 VEE
26 AGND
25 VCC
24 VFB
23 VSB
22 VRM
21 VIN
20 VST
19 VFT
18 VCC
17 AGND
16 VEE
15 CLK
TOP VIEW
________________________________________________________________ Maxim Integrated Products 1
For the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
1 page  
10-Bit, 40Msps, TTL-Output ADC
__________________________________________Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
TOTAL HARMONIC DISTORTION vs.
INPUT FREQUENCY
80
fS = 40Msps
70
SIGNAL-TO-NOISE vs.
INPUT FREQUENCY
80
fS = 40Msps
70
SIGNAL-TO-NOISE AND DISTORTION
vs. INPUT FREQUENCY
80
fS = 40Msps
70
60 60 60
50 50 50
40 40 40
30 30 30
20
1 10 100
INPUT FREQUENCY (MHz)
20 20
1 10 100 1 10 100
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
SNR, THD, SINAD vs.
SAMPLE RATE
80
fIN = 1MHz
70
SNR
60
50
SINAD
40
THD
30
20
1 10 100
SAMPLE RATE (Msps)
SNR, THD, SINAD vs.
TEMPERATURE
65
60 SNR
55
THD
SINAD
50
45
fS = 40Msps
fIN = 1MHz
40
-25 0 25 50
TEMPERATURE (°C)
75
SPECTRAL RESPONSE
0
fS = 40Msps
fIN = 1MHz
-30
-60
-90
-120
0
2468
INPUT FREQUENCY (MHz)
10
_______________Detailed Description
The MAX1161 requires few external components to
achieve the stated operation and performance. Figure 2
shows the typical interface requirements when using the
MAX1161 in normal circuit operation. The following sec-
tion provides a description of the pin functions, and out-
lines critical performance criteria to consider for
achieving optimal device performance.
Power Supplies and Grounding
The MAX1161 requires -5.2V and +5V analog supply
voltages. The +5V supply is common to analog VCC and
digital DVCC. A ferrite bead in series with each supply
line reduces the transient noise injected into the analog
VCC. These beads should be connected as close to the
device as possible. The connection between the beads
and the MAX1161 should not be shared with any other
device. Bypass each power-supply pin as close to the
device as possible. Use 0.1µF for VEE and VCC, and
0.01µF for DVCC (chip capacitors are recommended).
The MAX1161 has two grounds: AGND and DGND.
These internal grounds are isolated on the device. Use
ground planes for optimum device performance.
Use DGND for the DVCC return path (typically 40mA)
and for the return path for all digital output logic inter-
faces. Separate AGND and DGND from each other,
connecting them together only through a ferrite bead at
the device.
_______________________________________________________________________________________ 5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MAX1161.PDF ] | |
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