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PDF MAX1127 Data sheet ( Hoja de datos )
| Número de pieza | MAX1127 | |
| Descripción | Quad / 12-Bit / 65Msps / 1.8V ADC with Serial LVDS Outputs | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-3144; Rev 1; 3/04
Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs
General Description
The MAX1127 quad, 12-bit analog-to-digital converter
(ADC) features fully differential inputs, a pipelined
architecture, and digital error correction. This ADC is
optimized for low-power, high-dynamic performance for
medical imaging, communications, and instrumentation
applications. The MAX1127 operates from a 1.7V to
1.9V single supply and consumes only 563mW while
delivering a 69.6dB signal-to-noise ratio (SNR) at a
19.3MHz input frequency. In addition to low operating
power, the MAX1127 features a 675µA power-down
mode for idle periods.
An internal 1.24V precision bandgap reference sets the
ADC’s full-scale range. A flexible reference structure
allows the use of an external reference for applications
requiring increased accuracy or a different input volt-
age range.
A single-ended clock controls the conversion process.
An internal duty-cycle equalizer allows for wide varia-
tions in input-clock duty cycle. An on-chip phase-
locked loop (PLL) generates the high-speed serial
low-voltage differential signaling (LVDS) clock.
The MAX1127 provides serial LVDS outputs for data,
clock, and frame alignment signals. The output data is
presented in two’s complement or binary format.
Refer to the MAX1126 data sheet for a pin-compatible
40Msps version of the MAX1127.
The MAX1127 is available in a small, 10mm x 10mm x
0.9mm, 68-pin QFN package with exposed paddle and
is specified for the extended industrial (-40°C to +85°C)
temperature range.
Applications
Ultrasound and Medical Imaging
Positron Emission Tomography (PET) Imaging
Multichannel Communication Systems
Instrumentation
Features
♦ Four ADC Channels with Serial LVDS/SLVS
Outputs
♦ Excellent Dynamic Performance
69.6dB SNR at fIN = 19.3MHz
92dBc SFDR at fIN = 19.3MHz
-87dB Channel Isolation
♦ Ultra-Low Power
135mW per Channel (Normal Operation)
1.2mW Total (Shutdown Mode)
♦ Accepts 20% to 80% Clock Duty Cycle
♦ Self-Aligning Data-Clock to Data-Output Interface
♦ Fully Differential Analog Inputs
♦ Wide ±1.4VP-P Differential Input Voltage Range
♦ Internal/External Reference Option
♦ Test Mode for Digital Signal Integrity
♦ LVDS Outputs Support Up to 30in FR-4 Backplane
Connections
♦ Small, 68-Pin QFN with Exposed Paddle
♦ Evaluation Kit Available (MAX1127EVKIT)
Ordering Information
PART
MAX1127EGK
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
68 QFN 10mm x
x 10mm x 0.9mm
Pin Configuration
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
GND 1
IN0P 2
IN0N 3
GND 4
IN1P 5
IN1N 6
GND 7
AVDD 8
AVDD 9
AVDD 10
GND 11
IN2P 12
IN2N 13
GND 14
IN3P 15
IN3N 16
GND 17
EP
MAX1127
51 OUT0P
50 OUT0N
49 OVDD
48 OUT1P
47 OUT1N
46 OVDD
45 CLKOUTP
44 CLKOUTN
43 OVDD
42 FRAMEP
41 FRAMEN
40 OVDD
39 OUT2P
38 OUT2N
37 OVDD
36 OUT3P
35 OUT3N
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
QFN
10mm x 10mm x 0.9mm
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 1.8V, GND = 0, external VREFIO = 1.24V, INTREF = AVDD, CREFIO to GND = 0.1µF,
fCLK = 65MHz (50% duty cycle), DT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
AVDD Supply Current
SYMBOL
IAVDD
fIN =
19.3MHz at
-0.5dBFS
CONDITIONS
PDALL = 0, all channels
active
PDALL = 0, all channels
active, DT = 1
PDALL = 0, 1 channel active
PDALL = 0, PD[3:0] = 1111
PDALL = 1, global power
down, PD[3:0] =1111, no
clock input
MIN
TYP
257
MAX UNITS
295
257 mA
82
23
300 µA
OVDD Supply Current
IOVDD
fIN =
19.3MHz at
-0.5dBFS
PDALL = 0, all channels
active
PDALL = 0, all channels
active, DT = 1
PDALL = 0, 1 channel active
PDALL = 0, PD[3:0] = 1111
PDALL = 1, global power-
down, PD[3:0] =1111, no
clock input
56 65
72
42
37
375
mA
µA
CVDD Supply Current
ICVDD
Power Dissipation
PDISS
TIMING CHARACTERISTICS (Note 6)
Data Valid to CLKOUT Rise/Fall
tOD
CVDD is used only to bias ESD-protection
diodes on CLK input, Figure 2
fIN = 19.3MHz at -0.5dBFS
fCLK = 65MHz, Figure 5 (Notes 6 and 7)
0 mA
563 648 mW
(tSAMPLE/
24)
- 0.15
tSAMPLE/
24
(tSAMPLE/
24)
+ 0.15
ns
CLKOUT Output Width High
CLKOUT Output Width Low
FRAME Rise to CLKOUT Rise
tCH Figure 5
tCL Figure 5
tCF Figure 4 (Note 7)
tSAMPLE /
12
tSAMPLE /
12
(tSAMPLE/
24)
- 0.15
tSAMPLE/
24
(tSAMPLE/
24)
+ 0.15
ns
ns
ns
Sample CLK Rise to Frame Rise
tSF Figure 4 (Notes 7 and 8)
(tSAMPLE/ (tSAMPLE/ (tSAMPLE/
2) 2) 2)
+0.9 +1.3 +1.7
ns
_______________________________________________________________________________________ 5
5 Page 
Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs
Typical Operating Characteristics (continued)
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 1.8V, GND = 0, external VREFIO = 1.24V, INTREF = AVDD, differential input at -0.5dBFS,
fCLK = 65MHz (50% duty cycle), DT = low, CLOAD = 10pF, TA = +25°C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO
vs. CLOCK DUTY CYCLE
72
71 fIN = 5.301935MHz
70
69
68
67
66
65
64
63
62
30
40 50 60
CLOCK DUTY CYCLE (%)
70
SIGNAL-TO-NOISE + DISTORTION
vs. CLOCK DUTY CYCLE
72
71 fIN = 5.301935MHz
70
69
68
67
66
65
64
63
62
30
40 50 60
CLOCK DUTY CYCLE (%)
70
TOTAL HARMONIC DISTORTION
vs. CLOCK DUTY CYCLE
-75
fIN = 5.301935MHz
-80
SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK DUTY CYCLE
100
fIN = 5.301935MHz
95
-85 90
-90 85
-95 80
-100 75
-105
30
40 50 60
CLOCK DUTY CYCLE (%)
70
70
30
40 50 60
CLOCK DUTY CYCLE (%)
70
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet MAX1127.PDF ] | |
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