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PDF M82C288 Data sheet ( Hoja de datos )
| Número de pieza | M82C288 | |
| Descripción | BUS CONTROLLER FOR M80286 PROCESSORS | |
| Fabricantes | Intel | |
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M82C288
BUS CONTROLLER FOR M80286 PROCESSORS
(M82C288-10 M82C288-8 M82C288-6)
Military
Y Provides Commands and Controls for
Local and System Bus
Y Wide Flexibility in System
Configurations
Y Implemented in High Speed CHMOS III
Technology
Y Fully Compatible with the HMOS
M82288
Y Fully Static Device
Y Single a5V Supply
Y Available in 20 Pin Cerdip Package
(See Packaging Spec Order 231369)
The Intel M82C288 Bus Controller is a 20-pin CHMOS III component for use in M80C286 microsystems The
M82C288 is fully compatible with its predecessor the HMOS M82288 The bus controller is fully static and
supports a low power mode The bus controller provides command and control outputs with flexible timing
options Separate command outputs are used for memory and I O devices The data bus is controlled with
separate data enable and direction control signals
Two modes of operation are possible via a strapping option MULTIBUS Compatible bus cycles and high
speed bus cycles
20 Pin Cerdip Package
Figure 1 M82C288 Block Diagram
271077 – 1
271077 – 2
Figure 2 M82C288 Pin
Configuration
November 1991
Order Number 271077-006
1 page  
M82C288
The clock may be stopped in either state (HIGH
LOW) and held there indefinitely
Power dissipation is directly related to operating fre-
quency As the system frequency is reduced so is
the operating power When the clock is stopped to
the M82C288 power dissipation is at a minimum
This is useful for low-power and portable applica-
tions
FUNCTIONAL DESCRIPTION
Description
The M82C288 bus controller is used in M80286 sys-
tems to provide address latch control data trans-
ceiver control and standard level-type command
outputs The command outputs are timed and have
sufficient drive capabilities for large TTL buses and
meet all IEEE-796 requirements for MULTIBUS I A
special MULTIBUS I mode is provided to satisfy all
address data setup and hold time requirements
Command timing may be tailored to special needs
via a CMDLY input to determine the start of a com-
mand and READY to determine the end of a com-
mand
Connection to multiple buses are supported with a
latched enable input (CENL) An address decoder
can determine which if any bus controller should be
enabled for the bus cycle This input is latched to
allow an address decoder to take full advantage of
the pipelined timing on the M80286 local bus
Buses shared by several bus controllers are sup-
ported An AEN input prevents the bus controller
from driving the shared bus command and data
signals except when enabled by an external MULTI-
BUS I type bus arbiter
Separate DEN and DT R outputs control the data
transceivers for all buses Bus contention is eliminat-
ed by disabling DEN before changing DT R The
DEN timing allows sufficient time for tristate bus driv-
ers to enter 3-state OFF before enabling other driv-
ers onto the same bus
The term CPU refers to any M80286 processor or
M80286 support component which may become an
M80286 local bus master and thereby drive the
M82C288 status inputs
Processor Cycle Definition
Any CPU which drives the local bus uses an internal
clock which is one half the frequency of the system
clock (CLK) (see Figure 3) Knowledge of the phase
of the local bus master internal clock is required for
proper operation of the M80286 local bus The local
bus master informs the bus controller of its internal
clock phase when it asserts the status signals
Status signals are always asserted beginning in
Phase 1 of the local bus master’s internal clock
M82C284
(FOR REFERENCE)
271077 – 3
Figure 3 CLK Relationship to the Processor
Clock and Bus T-States
5
5 Page 
M82C288
are immediately forced inactive When CEN makes a
LOW to HIGH transition the commands and DEN
outputs immediately go to the appropriate state (see
timing waveforms) READY must still become active
to terminate a bus cycle if CEN remains LOW for a
selected bus controller (CENL was latched HIGH)
Some memory or I O systems may require more ad-
dress or write data setup time to command active
than provided by the basic command output timing
To provide flexible command timing the CMDLY in-
put can delay the activation of command outputs
The CMDLY input must be sampled LOW to activate
the command outputs CMDLY does not affect the
control outputs ALE MCE DEN and DT R
Figure 12 System Use of AEN and CENL
271077 – 12
11
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