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PDF M80C186XL16 Data sheet ( Hoja de datos )
| Número de pieza | M80C186XL16 | |
| Descripción | 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR | |
| Fabricantes | Intel | |
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M80C186XL20 16 12 10
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR
Y Low Power Full Static Version of
M80C186
Y Operation Modes
Enhanced Mode
DRAM Refresh Control Unit
Power-Save Mode
Direct Interface to 80C187
Compatible Mode
NMOS 80186 Pin-for-Pin
Replacement for Non-Numerics
Applications
Y Integrated Feature Set
Static Modular CPU
Clock Generator
2 Independent DMA Channels
Programmable Interrupt Controller
3 Programmable 16-Bit Timers
Dynamic RAM Refresh Control Unit
Programmable Memory and
Peripheral Chip Select Logic
Programmable Wait State Generator
Local Bus Controller
Power-Save Mode
System-Level Testing Support (High
Impedance Test Mode)
Y Completely Object Code Compatible
with Existing 8086 8088 Software and
Has 10 Additional Instructions over
8086 8088
Y Speed Versions Available
20 MHz (M80C186XL20)
16 MHz (M80C186XL16)
12 5 MHz (M80C186XL12)
10 MHz (M80C186XL)
Y Direct Addressing Capability to
1 MByte Memory and 64 Kbyte I O
Y Complete System Development
Support
All 8086 and 80C186 Software
Development Tools Can Be Used for
M80C186XL System Development
ASM 86 Assembler PL M-86
Pascal-86 Fortran-86 iC-86 and
System Utilities
In-Circuit-Emulator (ICETM-186)
Y Available in 68-Pin
Ceramic Pin Grid Array (PGA)
Y Military Temperature Range
b55 C to a125 C (TC)
The Intel M80C186XL is a Modular Core re-implementation of the M80C186 microprocessor It offers higher
speed and lower power consumption than the standard M80C186 but maintains 100% clock-for-clock func-
tional compatibility Packaging and pinout are also identical
271276 – 1
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1996
March 1995
Order Number 271276-002
1 page  
M80C186XL
Symbol
VCC
VSS
RESET
PGA
Pin No
9
43
26
60
57
X1 59
X2 58
CLKOUT
RES
56
24
TEST BUSY
47
Table 1 M80C186XL Pin Description
Type
Name and Function
I System Power a5 volt power supply
I
I System Ground
I
O RESET Output indicates that the M80C186XL CPU is being reset and
can be used as a system reset It is active HIGH synchronized with
the processor clock and lasts an integer number of clock periods
corresponding to the length of the RES signal Reset goes inactive 2
clockout periods after RES goes inactive When tied to the TEST
BUSY pin RESET forces the M80C186XL into enhanced mode
RESET is not floated during bus hold
I Crystal Inputs X1 and X2 provide external connections for a
O fundamental mode or third overtone parallel resonant crystal for the
internal oscillator X1 can connect to an external clock instead of a
crystal In this case minimize the capacitance on X2 The input or
oscillator frequency is internally divided by two to generate the clock
signal (CLKOUT)
O Clock Output provides the system with a 50% duty cycle waveform
All device pin timings are specified relative to CLKOUT CLKOUT is
active during reset and bus hold
I An active RES causes the M80C186XL to immediately terminate its
present activity clear the internal logic and enter a dormant state
This signal may be asynchronous to the M80C186XL clock The
M80C186XL begins fetching instructions approximately 6 clock
cycles after RES is returned HIGH For proper initialization VCC must
be within specifications and the clock signal must be stable for more
than 4 clocks with RES held LOW RES is internally synchronized
This input is provided with a Schmitt-trigger to facilitate power-on RES
generation via an RC network
I O The TEST pin is sampled during and after reset to determine whether
the M80C186XL is to enter Compatible or Enhanced Mode Enhanced
Mode requires TEST to be HIGH on the rising edge of RES and LOW
four CLKOUT cycles later Any other combination will place the
M80C186XL in Compatible Mode During power-up active RES is
required to configure TEST BUSY as an input A weak internal pullup
ensures a HIGH state when the input is not externally driven
TEST In Compatible Mode this pin is configured to operate as TEST
This pin is examined by the WAIT instruction If the TEST input is
HIGH when WAIT execution begins instruction execution will
suspend TEST will be resampled every five clocks until it goes LOW
at which time execution will resume If interrupts are enabled while the
M80C186XL is waiting for TEST interrupts will be serviced
BUSY In Enhanced Mode this pin is configured to operate as
BUSY The BUSY input is used to notify the M80C186XL of Math
Coprocessor activity Floating point instructions executing in the
M80C186XL sample the BUSY pin to determine when the Math
Coprocessor is ready to accept a new command BUSY is active
HIGH
5
5 Page 
M80C186XL
Bus Interface Unit
The M80C186XL provides a local bus controller to
generate the local bus control signals In addition it
employs a HOLD HLDA protocol for relinquishing
the local bus to other bus masters It also provides
outputs that can be used to enable external buffers
and to direct the flow of data on and off the local
bus
The bus controller is responsible for generating 20
bits of address read and write strobes bus cycle
status information and data (for write operations) in-
formation It is also responsible for reading data
from the local bus during a read operation Synchro-
nous and asynchronous ready input pins are provid-
ed to extend a bus cycle beyond the minimum four
states (clocks)
The M80C186XL bus controller also generates two
control signals (DEN and DT R) when interfacing to
external transceiver chips This capability allows the
addition of transceivers for simple buffering of the
multiplexed address data bus
During RESET the local bus controller will perform
the following action
Drive DEN RD and WR HIGH for one clock cy-
cle then float them
Drive S0–S2 to the inactive state (all HIGH) and
then float
Drive LOCK HIGH and then float
Float AD0–15 A16–19 BHE DT R
Drive ALE LOW
Drive HLDA LOW
RD QSMD UCS LCS MCS0 PEREQ MCS1
ERROR and TEST BUSY pins have internal pullup
devices which are active while RES is applied Ex-
cessive loading or grounding certain of these pins
causes the M80C186XL to enter an alternative
mode of operation
RD QSMD low results in Queue Status Mode
UCS and LCS low results in ONCE Mode
TEST BUSY low (and high later) results in En-
hanced Mode
M80C186XL PERIPHERAL
ARCHITECTURE
All the M80C186XL integrated peripherals are con-
trolled by 16-bit registers contained within an inter-
nal 256-byte control block The control block may be
mapped into either memory or I O space Internal
logic will recognize control block addresses and re-
spond to bus cycles An offset map of the 256-byte
control register block is shown in Figure 4
Chip-Select Ready Generation Logic
The M80C186XL contains logic which provides pro-
grammable chip-select generation for both memo-
ries and peripherals In addition it can be pro-
grammed to provide READY (or WAIT state) genera-
tion It can also provide latched address bits A1 and
A2 The chip-select lines are active for all memory
and I O cycles in their programmed areas whether
they be generated by the CPU or by the integrated
DMA unit
The M80C186XL provides 6 memory chip select out-
puts for 3 address areas upper memory lower
memory and midrange memory One each is provid-
ed for upper memory and lower memory while four
are provided for midrange memory
Relocation Register
OFFSET
FEH
DMA Descriptors Channel 1
DAH
D0H
DMA Descriptors Channel 0
CAH
C0H
Chip-Select Control Registers
A8H
A0H
Time 2 Control Registers
Time 1 Control Registers
Time 0 Control Registers
66H
60H
5EH
58H
56H
50H
Interrupt Controller Registers
3EH
20H
Figure 4 Internal Register Map
The M80C186XL provides a chip select called UCS
for the top of memory The top of memory is usually
used as the system memory because after reset the
M80C186XL begins executing at memory location
FFFF0H
11
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