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PDF M74HC4060 Data sheet ( Hoja de datos )
| Número de pieza | M74HC4060 | |
| Descripción | 14 STAGE BINARY COUNTER/OSCILLATOR | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M54HC4060
M74HC4060
14 STAGE BINARY COUNTER/OSCILLATOR
. HIGH SPEED
fMAX = 58 MHz (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 4 µA (MAX.) AT TA = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
|IOH| = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE
WITH 4060B
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HC4060F1R M74HC4060M1R
M74HC4060B1R M74HC4060C1R
PIN CONNECTIONS (top view)
DESCRIPTION
The M54/74HC4060 is a high speed CMOS 14-
STAGE BINARY COUNTER/OSCILLATOR fabri-
cated in silicon gate C2MOS technology. It has the
same high speed performance of LSTTL combined
with true CMOS low power consumption. It operates
ten times faster than metal-gate C2MOS IC (4060B)
with the same power dissipation.
The oscillator configuration allows design of either
RC or crystal oscillator circuits. A high level on the
CLEAR accomplishes the reset function, i.e. all
counter outputs are made low and the oscillator is
disabled.
A negative transition on the clock input increments
the counter. Ten kinds of divided output are pro-
vided ; 4 to 10 and 12 to 14 stage inclusive. The
maximum division available at Q12 is 1/16384 f os-
cillator.
The Ø1 input and the CLEAR input are equipped
with protection circuits against static discharge and
transient excess voltage.
March 1993
NC =
No Internal
Connection
1/12
1 page  
M 54/ M74H C4060
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
Test Conditions
VCC
(V)
TA = 25 oC
54HC and 74HC
Min. Typ. Max.
Value
-40 to 85 oC
74HC
Min. Max.
-55 to 125 oC
54HC
Min. Max.
Unit
tTLH Output Transition 2.0
tTHL Time
4.5
30 75
8 15
95 110
19 22 ns
6.0 7 13 16 19
tPLH Propagation
tPHL Delay Time
(øI - Q4)
2.0
4.5
6.0
170 300 375 450
41 60 75 90 ns
30 51 64 76
tPD Propagation Delay 2.0
Time Difference
(Qn- Qn+1)
4.5
6.0
32 75
7 15
5 13
95 110
19 22 ns
16 19
tPLH Propagation
tPHL Delay Time
(CLEAR - Qn)
2.0
4.5
6.0
85 195 245 295
23 39 49 59 ns
17 33 42 50
fMAX Maximum Clock 2.0
Frequency
4.5
6 12
5
4
30 50 24 20
ns
6.0 35 65 28 24
tW(H)
tW(L)
Minimum Pulse
Width (øI)
2.0
4.5
30 75
8 15
95 110
19 22 ns
6.0 7 13 16 19
tW(H)
Minimum Pulse
Width (CLEAR)
2.0
4.5
30 75
8 15
95 110
19 22 ns
6.0 7 13 16 19
tREM Minimum
Removal Time
2.0
4.5
40 100 125 150
10 20 25 30 ns
6.0 9 17 21 26
CIN Input Capacitance
5 10 10 10 pF
CPD (*) Power Dissipation
Capacitance
27
pF
(*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD •VCC •fIN + ICC
5/12
5 Page 
DIM.
A
B
D
d1
d2
E
e
e3
F
G
M
M1
M 54/ M74H C4060
MIN.
9.78
8.89
4.2
7.37
PLCC20 MECHANICAL DATA
mm
TYP.
2.54
0.56
1.27
5.08
0.38
1.27
1.14
MAX.
10.03
9.04
4.57
MIN.
0.385
0.350
0.165
8.38 0.290
0.101
inch
TYP.
0.100
0.022
0.050
0.200
0.015
0.050
0.045
MAX.
0.395
0.356
0.180
0.330
0.004
P027A
11/12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet M74HC4060.PDF ] | |
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