M68Z128WN Datasheet PDF - ST Microelectronics
| Part Number | M68Z128WN | |
| Description | 3V / 1 Mbit 128Kb x8 Low Power SRAM with Output Enable | |
| Manufacturers | ST Microelectronics | |
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M68Z128W
3V, 1 Mbit (128Kb x8) Low Power SRAM with Output Enable
s LOW VOLTAGE: 3.0V (+0.6V / –0.3V)
s 128Kb x 8 LOW POWER SRAM with OUTPUT
ENABLE
s EQUAL CYCLE and ACCESS TIMES: 70ns
s LOW VCC DATA RETENTION: 1.4V
s TRI-STATE COMMON I/O
s LOW ACTIVE and STANDBY POWER
s INTENDED for USE with ST ZEROPOWER®
and TIMEKEEPER® CONTROLLERS
DESCRIPTION
The M68Z128W is a 1 Mbit (1,048,576 bit) Fast
CMOS SRAM, organized as 131,072 words by 8
bits. The device features fully static operation re-
quiring no external clocks or timing strobes, with
equal address access and cycle times. It requires
a single 3.0V (+0.6V / –0.3V) supply, and all inputs
and outputs are TTL compatible. This device has
an automatic power-down feature, reducing the
power consumption by over 99% when deselect-
ed. The M68Z128W is available in the standard
450mil-wide TSOP type 1 package.
TSOP32 (N)
8 x 20mm
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
A0-A16
Address Inputs
DQ0-DQ7
Data Input/Output
E1 Chip Enable 1
E2 Chip Enable 2
G Output Enable
W Write Enable
VCC Supply Voltage
VSS Ground
NC Not Connected Internally
17
A0-A16
8
DQ0-DQ7
W
M68Z128W
E1
E2
G
VSS
AI01878B
March 2000
1/12
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M68Z128W
Table 7. Read and Standby Modes AC Characteristics
(TA = 0 to 70°C; VCC = 3.0V + 0.6V / –0.3V)
M68Z128W
Symbol
Parameter
-70 Unit
Min Max
tAVAV Read Cycle Time
70 ns
tAVQV (1) Address Valid to Output Valid
70 ns
tE1LQV (1) Chip Enable 1 Low to Output Valid
70 ns
tE2HQV (1) Chip Enable 2 High to Output Valid
70 ns
tGLQV (1) Output Enable Low to Output Valid
35 ns
tE1LQX (3) Chip Enable 1 Low to Output Transition
10 ns
tE2HQX (3) Chip Enable 2 High to Output Transition
10 ns
tGLQX (3) Output Enable Low to Output Transition
10 ns
tE1HQZ (2,3) Chip Enable 1 High to Output Hi-Z
0 25 ns
tE2LQZ (2,3) Chip Enable 2 Low to Output Hi-Z
0 25 ns
tGHQZ (2,3) Output Enable High to Output Hi-Z
0 25 ns
tAXQX (1) Address Transition to Output Transition
10 ns
tPU Chip Enable 1 Low or Chip Enable 2 High to Power Up
0
ns
tPD Chip Enable 1 High or Chip Enable 2 Low to Power Down
70 ns
Note: 1. CL = 50pF (see Figure 3).
2. CL = 5pF (see Figure 3).
3. At any given temperature and voltage condition, tEIHQZ + tEZHQZ is less than tEILQX and tEZLQX, tGHQZ is less than tGLQX for any
given device.
Figure 5. Address Controlled, Read Mode AC Waveforms
A0-A16
DQ0-DQ7
tAVQV
tAVAV
VALID
DATA VALID
tAXQX
AI01078
Note: E1 = Low, E2 = High, G = Low, W = High.
5/12
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for M68Z128WN electronic component. |
| Information | Total 12 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ M68Z128WN.PDF Datasheet ] | |
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