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PDF M36W108 Data sheet ( Hoja de datos )

Número de pieza M36W108
Descripción 8 Mbit 1Mb x8 / Boot Block Flash Memory and 1 Mbit 128Kb x8 SRAM Low Voltage Multi-Memory Product
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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No Preview Available ! M36W108 Hoja de datos, Descripción, Manual

M36W108T
M36W108B
8 Mbit (1Mb x8, Boot Block) Flash Memory and
1 Mbit (128Kb x8) SRAM Low Voltage Multi-Memory Product
NOT FOR NEW DESIGN
s M36W108T and M36W108B are replaced
respectively by the M36W108AT and
M36W108AB
s SUPPLY VOLTAGE
– VCCF = VCCS = 2.7V to 3.6V: for Program,
Erase and Read
s ACCESS TIME: 100ns
s LOW POWER CONSUMPTION
– Read: 40mA max. (SRAM chip)
– Stand-by: 30µA max. (SRAM chip)
– Read: 10mA max. (Flash chip)
– Stand-by: 100µA max. (Flash chip)
BGA
LBGA48 (ZM)
6 x 8 solder balls
LGA
LGA48 (ZN)
6 x 8 solder lands
FLASH MEMORY
s 8 Mbit (1Mb x 8) BOOT BLOCK ERASE
s PROGRAMMING TIME: 10µs typical
s PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-Byte
– Status Register bits and Ready/Busy Output
s MEMORY BLOCKS
– Boot Block (Top or Bottom location)
– Parameter and Main Blocks
s BLOCK, MULTI-BLOCK and CHIP ERASE
s ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
s 100,000 PROGRAM/ERASE CYCLES per
BLOCK
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code, M36W108T: D2h
– Device Code, M36W108B: DCh
Figure 1. Logic Diagram
VCCF VCCS
20
A0-A19
8
DQ0-DQ7
W
EF RB
M36W108T
G M36W108B
RP
E1S
E2S
SRAM
s 1 Mbit (128Kb x 8)
s POWER DOWN FEATURES USING TWO
CHIP ENABLE INPUTS
s LOW VCC DATA RETENTION: 2V
VSS
AI02509
May 1999
This is information on a product still in production but not recommended for new designs.
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M36W108 pdf
Figure 3. Internal Functional Arrangement
VCCF
VSS
RP
EF
A0-A19
W
G
8 Mbit
Flash Memory
(1Mb x 8)
VCCS
VSS
M36W108T, M36W108B
RB
DQ0-DQ7
A0-A16
E1S
E2S
1 Mbit SRAM
(128 Kb x 8)
AI02444
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M36W108 arduino
M36W108T, M36W108B
Table 10. Flash Status Register Bits (1)
DQ Name
Logic Level
Definition
Note
‘1’
Erase Complete or erase block
in Erase Suspend
7
Data
Polling
‘0’ Erase On-going
Indicates the P/E.C. status, check during
Program or Erase, and on completion before
Program Complete or data of checking bits DQ5 for Program or Erase
DQ non erase block during Erase Success.
Suspend
DQ Program On-going
‘-1-0-1-0-1-0-1-’ Erase or Program On-going
DQ Program Complete
6 Toggle Bit
Erase Complete or Erase
‘-1-1-1-1-1-1-1-’ Suspend on currently
addressed block
Successive reads output complementary
data on DQ6 while Programming or Erase
operations are on-going. DQ6 remains at
constant level when P/E.C. operations are
completed or Erase Suspend is
acknowledged.
5 Error Bit
‘1’
Program or Erase Error
This bit is set to ‘1’ in the case of
‘0’ Program or Erase On-going Programming or Erase failure.
4 Reserved
3
Erase
Time Bit
P/E.C. Erase operation has started. Only
‘1’ Erase Timeout Period Expired possible command entry is Erase Suspend
(ES).
‘0’
Erase Timeout Period
On-going
An additional block to be erased in parallel
can be entered to the P/E.C.
Chip Erase, Erase or Erase
Suspend on the currently
‘-1-0-1-0-1-0-1-’
addressed block.
Erase Error due to the
currently addressed block
2 Toggle Bit
(when DQ5 = ‘1’)
Program on-going, Erase
‘1’ on-going on another block or
Erase Complete
Indicates the erase status and allows to
identify the erased block.
DQ
Erase Suspend read on non
Erase Suspend block
1 Reserved
0 Reserved
Note: 1. Logic level ‘1’ is High, ‘0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
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