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PDF M35080BN Data sheet ( Hoja de datos )
| Número de pieza | M35080BN | |
| Descripción | 8 Kbit Serial SPI Bus EEPROM With Incremental Registers | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M35080
8 Kbit Serial SPI Bus EEPROM
With Incremental Registers
PRELIMINARY DATA
s Compatible with SPI Bus Serial Interface
(Positive Clock SPI Modes)
s Single Supply Voltage: 4.5 V to 5.5 V
s 5 MHz Clock Rate (maximum)
s Sixteen 16-bit Incremental Registers
s BYTE and PAGE WRITE (up to 32 Bytes)
(except for the Incremental Registers)
s Self-Timed Programming Cycle
s Hardware Protection of the Status Register
s Resizeable Read-Only EEPROM Area
s Enhanced ESD Protection
s 1 Million Erase/Write Cycles (minimum)
s 40 Year Data Retention (minimum)
DESCRIPTION
The M35080 device consists of 1024x8 bits of low
power
EEPROM,
fabricated
with
STMicroelectronics’ proprietary High Endurance
Double Polysilicon CMOS technology.
The device is accessed by a simple SPI-compati-
ble serial interface. The bus signals consist of a
serial clock input (C), a serial data input (D) and a
serial data output (Q), as shown in Table 1.
The device is selected when the chip select input
(S) is held low. Data is clocked in during the low to
high transition of the clock, C. Data is clocked out
during the high to low transition of the clock.
8
1
PSDIP8 (BN)
0.25 mm frame
8
1
SO8 (MN)
150 mil width
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
C Serial Clock
D Serial Data Input
Q Serial Data Output
S Chip Select
W Write Protect
VCC Supply Voltage
VSS Ground
DQ
C
M35080
S
W
VSS
AI02143
June 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/18
1 page  
Figure 5. Read EEPROM Array Operation Sequence
S
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30
C
INSTRUCTION
16 BIT ADDRESS
M35080
D 15 14 13 3 2 1 0
HIGH IMPEDANCE
Q
DATA OUT
76543210
MSB
AI01793
Note: 1. The most significant address bits, A15-A10, are treated as Don’t Care.
The latch becomes reset by any of the following
events:
– Power on
– WRDI instruction completion
– WRSR instruction completion
– WRITE instruction completion.
As soon as the WREN or WRDI instruction is re-
ceived, the memory device first executes the in-
struction, then enters a wait mode until the device
is deselected.
Read Status Register (RDSR)
The RDSR instruction allows the status register to
be read, and can be sent at any time, even during
a Write operation. Indeed, when a Write is in
progress, it is recommended that the value of the
Write-In-Progress (WIP) bit be checked. The value
in the WIP bit (whose position in the status register
is shown in Table 4) can be continuously polled,
before sending a new WRITE instruction. This can
be performed in one of two ways:
s Repeated RDSR instructions (each one
consisting of S being taken low, C being clocked
8 times for the instruction and 8 times for the
read operation, and S being taken high)
s A single, prolonged RDSR instruction
(consisting of S being taken low, C being
clocked 8 times for the instruction and kept
running for repeated read operations), as
shown in Figure 6.
The Write-In-Process (WIP) bit is read-only, and
indicates whether the memory is busy with a Write
operation. A ’1’ indicates that a write is in progress,
and a ’0’ that no write is in progress.
The Write Enable Latch (WEL) bit indicates the
status of the write enable latch. It, too, is read-only.
Its value can only be changed by one of the events
listed earlier, or as a result of executing WREN or
WRDI instruction. It cannot be changed using a
WRSR instruction. A ’1’ indicates that the latch is
set (the forthcoming Write instruction will be exe-
cuted), and a ’0’ that it is reset (and any forthcom-
ing Write instructions will be ignored).
The Block Protect (BP0 and BP1) bits indicate the
amount of the memory that is to be write-protect-
ed. These two bits are non-volatile. They are set
using a WRSR instruction.
During a Write operation (whether it be to the
memory area or to the status register), all bits of
the status register remain valid, and can be read
using the RDSR instruction. However, during a
Write operation, the values of the non-volatile bits
Table 6. Memory Mapping
Address
Protection
000h-01Fh
Incremental area: a word (2 bytes) can be written only if the new value to write is larger
than the value already stored
020h-3FFh
No specific protection except the one as of Table 7
5/18
5 Page 
Figure 12. Page Write Operation Sequence
M35080
S
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
C
INSTRUCTION
16 BIT ADDRESS
DATA BYTE 1
D 15 14 13 3 2 1 0 7 6 5 4 3 2 1 0
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
DATA BYTE 2
DATA BYTE 3
DATA BYTE N
D
7654321076543210
6543210
AI01796
Note: 1. The most significant address bits, A15-A10, are treated as Don’t Care.
2. The number of clock pulses must be a multiple of 8. Otherwise, the write is aborted.
POWER ON STATE
After power-on, the memory device is in the follow-
ing state:
– low power stand-by state
– deselected (after power-on, a high-to-low transi-
tion is required on the S input before any opera-
tions can be started).
– the WEL bit is reset
– the SRWD, BP1 and BP0 bits of the status reg-
ister are unchanged from the previous power-
down (they are non-volatile bits).
Table 8. Initial Status Register Format
b7
0 001 0 0 0
b0
0
INITIAL DELIVERY STATE
The device is delivered with the memory array in a
fully erased state. With the exception of the first 32
bytes, all data bits are set to ‘1’, and hence all data
bytes are at FFh. The first 32 bytes are set to all
‘0’s, and hence the first 16 words at 0000h.
The status register bits are initialized to ‘0’, except
for bit b4, which is set to ‘1’, as shown in Table 8.
11/18
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