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PDF M34C02 Data sheet ( Hoja de datos )
| Número de pieza | M34C02 | |
| Descripción | 2 Kbit Serial IC Bus EEPROM For DIMM Serial Presence Detect | |
| Fabricantes | ST Microelectronics | |
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M34C02
2 Kbit Serial I²C Bus EEPROM
For DIMM Serial Presence Detect
s Two Wire I2C Serial Interface
Supports 400 kHz Protocol
s Single Supply Voltage:
– 2.5V to 5.5V for M34C02-W
– 2.2V to 5.5V for M34C02-L
s Software Data Protection for lower 128 bytes
s BYTE and PAGE WRITE (up to 16 bytes)
s RANDOM and SEQUENTIAL READ Modes
s Self-Timed Programming Cycle
s Automatic Address Incrementing
s Enhanced ESD/Latch-Up Protection
s 1 Million Erase/Write Cycles (minimum)
s 40 Year Data Retention (minimum)
DESCRIPTION
The M34C02 is a 2 Kbit serial EEPROM memory
able to lock permanently the data in its first half
(from location 00h to 7Fh). This facility has been
designed specifically for use in DRAM DIMMs
(dual interline memory modules) with Serial
Presence Detect. All the information concerning
the DRAM module configuration (such as its
access speed, its size, its organization) can be
kept write protected in the first half of the memory.
This bottom half of the memory area can be write-
protected using a specially designed software
write protection mechanism. By sending the
device a specific sequence, the first 128 bytes of
Table 1. Signal Names
E0, E1, E2
Chip Enable Inputs
SDA
Serial Data/Address Input/
Output
SCL
Serial Clock
WC Write Control
VCC
VSS
Supply Voltage
Ground
8
1
PSDIP8 (BN)
0.25 mm frame
88
1
SO8 (MN)
150 mil width
1
TSSOP8 (DW)
169 mil width
Figure 1. Logic Diagram
VCC
3
E0-E2
SCL
WC
M34C02
SDA
VSS
AI01931
December 1999
1/19
1 page  
M34C02
Table 4. Operating Modes
Mode
RW bit
Current Address Read
1
Random Address Read
0
1
Sequential Read
1
Byte Write
0
Page Write
Note: 1. X = VIH or VIL.
0
WC 1
X
X
X
X
VIL
VIL
Bytes
1
1
≥1
1
≤ 16
Initial Sequence
START, Device Select, RW = ‘1’
START, Device Select, RW = ‘0’, Address
reSTART, Device Select, RW = ‘1’
Similar to Current or Random Address Read
START, Device Select, RW = ‘0’
START, Device Select, RW = ‘0’
command triggers the internal EEPROM write
cycle.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a
successful byte transfer. The bus transmitter,
whether it be master or slave, releases the SDA
bus after sending eight bits of data. During the 9th
clock pulse period, the receiver pulls the SDA bus
low to acknowledge the receipt of the eight data
bits.
Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high
transition, and the data must change only when
the SCL line is low.
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is
further subdivided into: a 4-bit Device Type
Identifier, and a 3-bit Chip Enable “Address” (E2,
E1, E0).
To address the memory array, the 4-bit Device
Type Identifier is 1010b. To address the Protection
Register, it is 0110b.
If all three chip enable inputs are connected, up to
eight memory devices can be connected on a
single I2C bus. Each one is given a unique 3-bit
code on its Chip Enable inputs. When the Device
Select Code is received on the SDA bus, the
memory only responds if the Chip Select Code is
the same as the pattern applied to its Chip Enable
pins.
The 8th bit is the read or write bit (RW). This bit is
set to ‘1’ for read and ‘0’ for write operations. If a
match occurs on the Device Select Code, the
corresponding memory gives an acknowledgment
on the SDA bus during the 9th bit time. If the
memory does not match the Device Select code, it
will deselect itself from the bus, and go into stand-
by mode.
Write Operations
Following a START condition the master sends a
Device Select Code with the RW bit set to ’0’, as
shown in Table 4. The memory acknowledges this,
and waits for an address byte. The memory
responds to the address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if the WC
input pin is taken high.
Byte Write
In the Byte Write mode, after the Device Select
Code and the address byte, the master sends one
data byte. If the addressed location is in a write
protected area, the memory replies with a NoAck,
and the location is not modified. If, instead, the
addressed location is not in a write protected area,
the memory replies with an Ack. The master
terminates the transfer by generating a STOP
condition.
Page Write
The Page Write mode allows up to 16 bytes to be
written in a single write cycle, provided that they
are all located in the same ’row’ in the memory:
that is the most significant memory address bits
(b7-b4) are the same. If more bytes are sent than
will fit up to the end of the row, a condition known
as ‘roll-over’ occurs. Data starts to become
overwritten (in a way not formally specified in this
data sheet).
The master sends from one up to 16 bytes of data,
each of which is acknowledged by the memory if
the WC pin is low. If the WC pin is high, the
contents of the addressed memory location are
not modified. After each byte is transferred, the
internal byte address counter (the 4 least
5/19
5 Page 
M34C02
Table 6. DC Characteristics
(TA = –40 to 85 °C; VCC = 2.5 to 5.5 V, 2.2 to 5.5 V)
Symbol
Parameter
Test Condition
Min.
ILI
Input Leakage
Current
SCL, SDA
0 V ≤ VIN ≤ VCC
ILO Output Leakage Current
0 V ≤ VOUT ≤ VCC, SDA in Hi-Z
-W or -L series VCC =5V, fc=400kHz (rise/fall time < 30ns)
ICC Supply Current
-W series VCC =2.5V, fc=400kHz (rise/fall time < 30ns)
-L series VCC =2.2V, fc=400kHz (rise/fall time < 30ns)
-W or -L series
ICC1
Supply Current
(Stand-by)
-W series
-L series
VIN = VSS or VCC , VCC = 5 V
VIN = VSS or VCC , VCC = 2.5 V
VIN = VSS or VCC , VCC = 2.2 V
VIL
Input Low
Voltage
SCL, SDA
E0, E1, E2
WC
– 0.3
– 0.3
– 0.3
VIH
Input High
Voltage
SCL, SDA
E0, E1, E2
WC
0.7VCC
0.7VCC
0.7VCC
VOL
Output Low
Voltage
-W or -L series
-W series
-L series
IOL = 3 mA, VCC = 5 V
IOL = 2.1 mA, VCC = 2.5 V
IOL = 2.1 mA, VCC = 2.2 V
Max. Unit
± 2 µA
±2
2
1
1
1
0.5
0.5
0.3VCC
0.3VCC
0.5
VCC+1
VCC+1
VCC+1
0.4
0.4
0.4
µA
mA
mA
mA
µA
µA
µA
V
V
V
V
V
V
V
V
V
Table 7. AC Measurement Conditions
Input Rise and Fall Times
≤ 50 ns
Input Pulse Voltages
0.2VCC to 0.8VCC
Input and Output Timing
Reference Voltages
0.3VCC to 0.7VCC
Figure 11. AC Testing Input Output Waveforms
0.8VCC
0.7VCC
0.2VCC
0.3VCC
AI00825
Table 8. Input Parameters 1(TA = 25 °C, f = 400 kHz)
Symbol
Parameter
Test Condition
CIN Input Capacitance (SDA)
CIN
ZWCL
Input Capacitance (other pins)
WC Input Impedance
VIN < 0.5 V
ZWCH
WC Input Impedance
VIN > 0.7VCC
tNS Low Pass Filter Input Time
Constant (SCL and SDA)
Note: 1. Sampled only, not 100% tested.
Min.
5
500
100
Max.
8
6
20
500
Unit
pF
pF
kΩ
kΩ
ns
11/19
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet M34C02.PDF ] | |
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