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PDF M30222 Data sheet ( Hoja de datos )

Número de pieza M30222
Descripción SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Fabricantes Mitsubishi 
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dUevnedloSeprpmeenctifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
The M30222 single-chip microcomputers are built using the high-performance silicon gate CMOS process
using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP. These single-chip
microcomputers operate using sophisticated instructions featuring a high-level of instruction efficiency and
are capable of executing instructions at high speed. They also feature a built-in multiplier and DMAC,
making them ideal for controlling office, communications, industrial equipment, and other high-speed pro-
cessing applications.
The M30222 group includes a range of products with various package types.
Features
• Memory capacity ......................................... Flash ROM 260 Kbytes
...................................................................... RAM 20 Kbytes
• Shortest instruction execution time ............. 62.5ns (f(XIN)=16MHZ)
• Supply voltage ............................................ 2.7 to 5.5V
• Low power consumption ............................. TBD
• Interrupts ..................................................... 25 internal and 8 external interrupt sources
4 software interrupt sources
7 levels (including key input interrupt)
• Multifunction 16-bit timer ............................. 5 output timers, 6 input timers, three phase motor control, real-time port
• Serial I/O ..................................................... 5 channel
3 for UART or clock synchronous (1 channel for I2C or SPI)
2 for clock synchronous
• DMAC ........................................................... 2 channels (trigger: 24 sources)
• A-D converter ............................................... 10 bits X 8 channels (expandable up to 10 channels)
• D-A converter ............................................... 8 bits X 2 channels
• CRC calculation circuit ................................. 1 circuit
• Watchdog timer ............................................ 1 timer
• Key-on Wake up ........................................... 8 inputs
• Programmable I/O ........................................ 54 lines
• Input port ...................................................... 1 line (P83 shared with NMI pin)
• Clock generating circuit ............................... 2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
•LCD Drive ...................................................... 1/2, 1/3 bias
4 common outputs
40 segment outputs
Built-in charge pump
1/2, 1/3, 1/4 duty
Specifications written in this manual
are believed to be accurate but are
not guaranteed to be entirely error
free. They may be changed for func-
tional or performance improvements.
Expansion CLK output Please make sure your manual is the
Static/direct drive mode latest version.
Applications
Audio, cameras, office, industrial, communications and, portable equipment
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M30222 pdf
dUevnedloSeprpmeenctifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Performance Outline
Table 1.1. Performance outline of the M30222 group
Parameters
Functions
Number of basic instructions
Shortest instruction execution time
Memory size
ROM
RAM
Input/Output
P3-P4, P6-P10
except P83
I/O
P83 I
Multifunctional
timer
TA0, TA1, TA2, TA3, TA4
TB0, TB1, TB2, TB3, TB4, TB5
Serial I/O
UART0, UART1, UART2
SIO3, SIO4
A-D converter
D-A converter
CRC calculation circuit
Watchdog timer
Interrupts
Clock generating circuit
Supply voltage
Power consumption
I/O characteristics I/O withstand voltage
Output current
P3, P4
P6-P10
Device configuration
Package
LCD
COM0 to COM3
SEG0 to SEG39
91
62.5ns f(Xin) = 16MHz
260K bytes
20K bytes
8 bits x 6, 7 bits x 1
1 bit x 1
16 bits x 5
16 bits x 6, three-phase motor control
(UART or clock synchronous) x 3, or I2C x 1
(Clock synchronous) x 2
10 bits x (8 + 2) channels
8 bits x 2
CRC-CCITT
15 bits x 1 (with prescaler)
25 external, 8 internal sources, 4 software, 7 levels
2 built-in clock generation circuits
2.7 to 5.5V f(Xin) = 16 MHz, without software wait
TBD
5.5V
0.1 mA (high output), 2.5 mA (low output)
5 mA at 5V (excluding pins P70, P71, P83)
CMOS high performance silicon gate
100-pin plastic mold QFP
4 lines
40 lines (16 lines shared with I/O ports)
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M30222 arduino
deUvnedloepr ment
Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
CPU
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each
configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack
pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.7 shows the flag
register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is cleared to
“0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to “0”
when the interrupt is acknowledged.
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected when this
flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
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