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Mitsubishi - 64M bit Synchronous DRAM

Numéro de référence M2V64S40BTP-6
Description 64M bit Synchronous DRAM
Fabricant Mitsubishi 
Logo Mitsubishi 





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M2V64S40BTP-6 fiche technique
PC133 SDRAM (Rev.0.5)
Oct. '99
64M bit Synchronous DRAM
MITSUBISHI LSIs
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
PRELIMINARY
Some of contents are described for general products and are
subject to change without notice.
DESCRIPTION
M2V64S20BTP is organized as 4-bank x4,194,304-word x 4-bit,and M2V64S30BTP is organized
as 4-bank x 2097152-word x 8-bit ,and M2V64S40BTP is organized as 4-bank x 1048576-word x 16-bit
Synchronous DRAM with LVTTL interface. All inputs and outputs are referenced to the rising edge of
CLK. M2V64S20BTP,M2V64S30BTP,M2V64S40BTP achieves very high speed data rates up to
133MHz, and is suitable for main memory or graphic memory in computer systems.
FEATURES
ITEM
tCLK Clock Cycle Time
(Min.)
tRAS Active to Precharge Command Period
(Min.)
tRCD Row to Column Delay
(Min.)
tAC Access Time from CLK
(Max.) (CL=3)
tRC Ref/Active Command Period
Icc1 Operation Current (Max.) [Single Bank]
(Min.)
Icc6 Self Refresh Current
(Max.)
M2V64S20TP
M2V64S30TP
M2V64S40TP
-6
7.5ns
45ns
20.0ns
5.4ns
67.5ns
120mA
1mA
- Single 3.3V ±0.3V power supply
- Max. Clock frequency -6 : 133MHz [PC133<3-3-3> ]
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 4096 refresh cycles /64ms
- LVTTL Interface
- Package 400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
MITSUBISHI ELECTRIC
1

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