DataSheetWiki


M2V64S30DTP-8L fiches techniques PDF

Mitsubishi - 64M Synchronous DRAM

Numéro de référence M2V64S30DTP-8L
Description 64M Synchronous DRAM
Fabricant Mitsubishi 
Logo Mitsubishi 





1 Page

No Preview Available !





M2V64S30DTP-8L fiche technique
MITSUBISHI LSIs
SDRAM (Rev.3.2)
Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT)
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 8-BIT)
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
PRELIMINARY
Some of contents are described for general products and are
subject to change w ithout notice.
DESCRIPTION
M 2V64S20DTP is a 4-bank x 4,194,304-word x 4-bit,
M 2V64S30DTP is a 4-bank x 2,097,152-word x 8-bit,
M 2V64S40DTP is a 4-bank x 1,048,576-word x 16-bit,
synchronous DRAM , with LVTTL interface. All inputs and outputs are referenced to the rising edge
of CLK. M 2V64S20DTP, M 2V64S30DTP and M 2V64S40DTP achieve very high speed data rate up
to 133MHz for -6, and are suitable for main memory or graphic memory in computer systems.
FEATURES
ITEM
tCLK
tRAS
tRCD
Clock Cycle T ime
Active to Precharge Command Period
Row to Column Delay
(Min.)
(Min.)
(Min.)
tAC Access Time from CLK
(Max.) (CL=3)
tRC Ref /Active Command Period
(Min.)
Icc1 Operation Current
(Max.)
(Single Bank)
V64S20D
V64S30D
V64S40D
Icc6 Self Refresh Current
(Max.)
M2V64S20/30/40DTP
-6 -7
-8
7.5ns
45ns
20ns
10ns
50ns
20ns
10ns
50ns
20ns
5.4ns
67.5ns
6ns
70ns
6ns
70ns
75mA 70mA
70mA
75mA 70mA
70mA
85mA 80mA
80mA
1mA
1mA
1mA
- Single 3.3v±0.3V power supply
- Max. Clock frequency -6:133MHz<3-3-3>, -7:100MHz<2-2-2>, -8:100MHz<3-2-2>
- Fully Synchronous operation referenced to clock rising edge
- 4 bank operation controlled by BA0 & BA1 (Bank Address)
- /CAS latency- 2 and 3 (programmable)
- Burst length- 1, 2, 4, 8 and full page (programmable)
- Burst type- sequential and interleave (programmable)
- Byte Control- DQM L and DQMU for M2V64S40DTP
- Random column access
- Auto p recharge and All bank precharge controlled by A10
- Auto refresh and Self refresh
- 4096 refresh cycles every 64ms
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
MITSUBISHI ELECTRIC
1

PagesPages 30
Télécharger [ M2V64S30DTP-8L ]


Fiche technique recommandé

No Description détaillée Fabricant
M2V64S30DTP-8 64M Synchronous DRAM Mitsubishi
Mitsubishi
M2V64S30DTP-8L 64M Synchronous DRAM Mitsubishi
Mitsubishi

US18650VTC5A

Lithium-Ion Battery

Sony
Sony
TSPC106

PCI Bus Bridge Memory Controller

ATMEL
ATMEL
TP9380

NPN SILICON RF POWER TRANSISTOR

Advanced Semiconductor
Advanced Semiconductor


www.DataSheetWiki.com    |   2020   |   Contactez-nous  |   Recherche