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PDF M2V28S30ATP Data sheet ( Hoja de datos )
| Número de pieza | M2V28S30ATP | |
| Descripción | 128M Synchronous DRAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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SDRAM (Rev. 1.0E)
Nov. '99
MITSUBISHI LSIs
128M Synchronous DRAM
M2V28S20ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 8,388,608-WORD x 4-BIT)
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 8-BIT)
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT)
PRELIMINARY
Some of contents are described for general products and are
subject to change without notice.
DESCRIPTION
M2V28S20ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL
interface and M2V28S30ATP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40ATP is organized
as 4-bank x 2,097,152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.
M2V28S20ATP,M2V28S30ATP,M2V28S40ATP achieves very high speed data rates up to 133MHz,
and is suitable for main memory or graphic memory in computer systems.
FEATURES
ITEM
tCLK
tRAS
tRCD
tAC
tRC
Icc1
Clock Cycle Time
(Min.)
Active to Precharge Command Period
Row to Column Delay
Access Time from CLK
Ref/Active Command Period
Operation Current
(Max.)
(Single Bank)
(Min.)
(Min.)
(Max.) (CL=3)
(Min.)
V28S20
V28S30
V28S40
Icc6 Self Refresh Current
(Max.)
M2V28S20/30/40ATP
-6 -7
-8
7.5ns
10ns 10ns
45ns 50ns
50ns
20ns
5.4ns
67.5ns
20ns
6ns
70ns
20ns
6ns
70ns
100mA 95mA
95mA
110mA 100mA 100mA
130mA 120mA 120mA
2mA
2mA
2mA
- Single 3.3V ±0.3V power supply
- Max. Clock frequency -6:PC133<3-3-3> / -7:PC100<2-2-2> / -8:PC100<3-2-2>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQML and DQMU (M2V28S40ATP)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 4096 refresh cycles /64ms
- LVTTL Interface
- Package
M2V28S20ATP/30ATP/40ATP
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
MITSUBISHI ELECTRIC
1
1 page  
SDRAM (Rev. 1.0E)
Nov. '99
MITSUBISHI LSIs
128M Synchronous DRAM
M2V28S20ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 8,388,608-WORD x 4-BIT)
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 8-BIT)
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT)
BASIC FUNCTIONS
The M2V28S30ATP provides basic functions, bank (row) activate, burst read / write, bank
(row) precharge, and auto / self refresh.
Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In
addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option,
respectively.
To know the detailed definition of commands, please see the command truth table.
CLK
/CS
/RAS
/CAS
/WE
CKE
A10
Chip Select : L=select, H=deselect
Command
Command define basic commands
Command
Refresh Option @ refresh command
Precharge Option @ precharge or read/write command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data
appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst
read (auto-precharge, READA).
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to
be written is set by burst length. When A10 =H at this command, the bank is deactivated after the
burst write (auto-precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates
burst read / write operation. When A10 =H at this command, all banks are deactivated (precharge all,
PREA ).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are
generated internally. After this command, the banks are precharged automatically.
MITSUBISHI ELECTRIC
5
5 Page 
SDRAM (Rev. 1.0E)
Nov. '99
MITSUBISHI LSIs
128M Synchronous DRAM
M2V28S20ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 8,388,608-WORD x 4-BIT)
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 8-BIT)
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT)
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE Address
Command Action
WRITE
H X X XX
RECOVERING
L H H HX
DESEL NOP
NOP NOP
L H H L BA
TBST ILLEGAL*2
READ /
L H L X BA, CA, A10
ILLEGAL*2
WRITE
L L H H BA, RA
ACT ILLEGAL*2
L L H L BA, A10
PRE / ILLEGAL*2
PREA
L L L HX
L L L L Op-Code,
Mode-Add
REFA ILLEGAL
MRS ILLEGAL
REFRESHING H X X X X
DESEL NOP (Idle after tRC)
L H H HX
NOP NOP (Idle after tRC)
L H H L BA
TBST ILLEGAL
READ /
L H L X BA, CA, A10
ILLEGAL
WRITE
L L H H BA, RA
ACT ILLEGAL
L L H L BA, A10
PRE /
PREA
ILLEGAL
L L L HX
Op-Code,
L L LL
Mode-Add
REFA ILLEGAL
MRS ILLEGAL
MITSUBISHI ELECTRIC
11
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