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M2V12D20TP-10L fiches techniques PDF

Mitsubishi - 512M Double Data Rate Synchronous DRAM

Numéro de référence M2V12D20TP-10L
Description 512M Double Data Rate Synchronous DRAM
Fabricant Mitsubishi 
Logo Mitsubishi 





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M2V12D20TP-10L fiche technique
DDR SDRAM (Rev.1.1)
Feb.ME'0LITE2SCUTBRIISCHI
MITSUBISHI LSIs
M2S12D20/ 30TP -75, -75L, -10, -10L
512M Double Data Rate Synchronous DRAM
DESCRIPTION
M2S12D20TP is a 4-bank x 33,554,432-word x 4-bit,
M2S12D30TP is a 4-bank x 16,777,216-word x 8-bit,
double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are
referenced to the rising edge of CLK. Input data is registered on both edges of data strobes, and
output data and data strobe are referenced on both edges of CLK. The M2S12D20/30TP achieve
very high speed data rate up to 133MHz, and are suitable for main memory in computer systems.
FEATURES
- Vdd=Vddq=2.5V+0.2V
- Double data rate architecture; two data transfers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/received with data
- Differential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions
- Commands are entered on each positive CLK edge;
- data and data mask are referenced to both edges of DQS
- 4 bank operations are controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst type- sequential / interleave (programmable)
- Auto precharge / All bank precharge is controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11-12(x4)/ A0-9,11(x8)
SSTL_2 Interface
- 400-mil, 66-pin Thin Small Outline Package (TSOP II)
- JEDEC standard
- Low Power for the Self Refresh Current ICC6 :4mA (-75L,-10L)
Operating Frequencies
Speed Grade
-75 / -75L
-10 / -10L
Clock Rate
CL=2 *
CL=2.5 *
100MHz
133MHz
100MHz
125MHz
* CL = CAS(Read) Latency
Contents are subject to change without notice.
MITSUBISHI ELECTRIC
-1-

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