M29W400DT70ZA1F Datasheet PDF - ST Microelectronics
| Part Number | M29W400DT70ZA1F | |
| Description | 4 Mbit (512Kb x8 or 256Kb x16 / Boot Block) 3V Supply Flash Memory | |
| Manufacturers | ST Microelectronics | |
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M29W400DT
M29W400DB
4 Mbit (512Kb x8 or 256Kb x16, Boot Block)
3V Supply Flash Memory
PRELIMINARY DATA
FEATURES SUMMARY
s SUPPLY VOLTAGE
– VCC = 2.7V to 3.6V for Program, Erase and
Read
s ACCESS TIME: 45, 55, 70ns
s PROGRAMMING TIME
– 10µs per Byte/Word typical
s 11 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 8 Main Blocks
s PROGRAM/ERASE CONTROLLER
– Embedded Byte/Word Program algorithms
s ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
s UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
s TEMPORARY BLOCK UNPROTECTION
MODE
s LOW POWER CONSUMPTION
– Standby and Automatic Standby
s 100,000 PROGRAM/ERASE CYCLES per
BLOCK
s ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Top Device Code M29W400DT: 00EEh
– Bottom Device Code M29W400DB: 00EFh
Figure 1. Packages
SO44 (M)
TSOP48 (N)
12 x 20mm
FBGA
TFBGA48 (ZA)
6 x 9mm
February 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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M29W400DT, M29W400DB
SUMMARY DESCRIPTION
The M29W400D is a 4 Mbit (512Kb x8 or 256Kb
x16) non-volatile memory that can be read, erased
and reprogrammed. These operations can be per-
formed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode where it can be read in the same way
as a ROM or EPROM.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
The blocks in the memory are asymmetrically ar-
ranged, see Figures 6 and 7, Block Addresses.
The first or last 64 Kbytes have been divided into
four additional blocks. The 16 Kbyte Boot Block
can be used for small initialization code to start the
microprocessor, the two 8 Kbyte Parameter
Blocks can be used for parameter storage and the
remaining 32K is a small Main Block where the ap-
plication may be stored.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in SO44, TSOP48 (12 x
20mm) and TFBGA48 (0.8mm pitch) packages.
The memory is supplied with all the bits erased
(set to ’1’).
Figure 2. Logic Diagram
VCC
18
A0-A17
15
DQ0-DQ14
W DQ15A–1
M29W400DT
E M29W400DB BYTE
G RB
RP
VSS
AI06853
Table 1. Signal Names
A0-A17
Address Inputs
DQ0-DQ7 Data Inputs/Outputs
DQ8-DQ14 Data Inputs/Outputs
DQ15A–1 Data Input/Output or Address Input
E Chip Enable
G Output Enable
W Write Enable
RP Reset/Block Temporary Unprotect
RB
Ready/Busy Output
(not available on SO44 package)
BYTE
Byte/Word Organization Select
VCC Supply Voltage
VSS Ground
NC Not Connected Internally
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