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PDF 74VHCT74A Data sheet ( Hoja de datos )
| Número de pieza | 74VHCT74A | |
| Descripción | Dual D-Type Flip-Flop with Preset and Clear | |
| Fabricantes | Fairchild Semiconductor | |
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May 2008
74VHCT74A
Dual D-Type Flip-Flop with Preset and Clear
Features
n High speed: fMAX = 160MHz (Typ.) at TA = 25°C
n High noise immunity: VIH = 2.0V, VIL = 0.8V
n Power down protection is provided on all inputs and
outputs
n Low power dissipation: ICC = 2µA (Max.) at TA = 25°C
n Pin and function compatible with 74HCT74
General Description
The VHCT74A is an advanced high speed CMOS Dual
D-Type Flip-Flop fabricated with silicon gate CMOS tech-
nology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. The signal level applied to
the D INPUT is transferred to the Q OUTPUT during the
positive going transition of the CK pulse. CLR and PR
are independent of the CK and are accomplished by set-
ting the appropriate input LOW.
Protection circuits ensure that 0V to 7V can be applied to
the input pins without regard to the supply voltage and to
the output pins with VCC = 0V. These circuits prevent
device destruction due to mismatched supply and input/
output voltages. This device can be used to interface 3V
to 5V systems and two supply systems such as battery
backup.
Ordering Information
Order Number
Package
Number
Package Description
74VHCT74AM
74VHCT74ASJ
74VHCT74AMTC
M14A
M14D
MTC14
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©2008 Fairchild Semiconductor Corporation
74VHCT74A Rev. 1.4.0
www.fairchildsemi.com
1 page  
AC Operating Requirements
Symbol
tW(L), tW(H)
tW(L)
tS
tH
tREM
Parameter
Minimum Pulse Width (CK)
Minimum Pulse Width (CLR, PR)
Minimum Setup Time
Minimum Hold Time
Minimum Removal Time (CLR, PR)
VCC (V)
5.0 ± 0.5
5.0 ± 0.5
5.0 ± 0.5
5.0 ± 0.5
5.0 ± 0.5
TA = 25°C
TA = –40°C
to +85°C
Guaranteed
Typ. Minimum
5.0 5.0
5.0 5.0
5.0 5.0
00
3.5 3.5
Units
ns
ns
ns
ns
ns
©2008 Fairchild Semiconductor Corporation
74VHCT74A Rev. 1.4.0
5
www.fairchildsemi.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet 74VHCT74A.PDF ] | |
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