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PDF 74VHC541SJ Data sheet ( Hoja de datos )
| Número de pieza | 74VHC541SJ | |
| Descripción | Octal Buffer/Line Driver with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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August 1993
Revised April 1999
74VHC541
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The VHC541 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation.
The VHC541 is an octal buffer/line driver designed to be
employed as memory and address drivers, clock drivers
and bus oriented transmitter/receivers.
This device is similar in function to the VHC244 while pro-
viding flow-through architecture (inputs on opposite side
from outputs). This pinout arrangement makes this device
especially useful as an output port for microprocessors,
allowing ease of layout and greater PC board density.
An input protection circuit insures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s High Speed: tPD = 3.5 ns (typ) at VCC = 5V
s Low power dissipation: ICC = 4 µA (max) at TA = 25°C
s High noise immunity: VNIH = VNIL = 28% VCC (min)
s Power down protection is provided on all inputs
s Low noise: VOLP = 0.9V (typ)
s Pin and function compatible with 74HC541
Ordering Code:
Order Number Package Number
Package Description
74VHC541M
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74VHC541SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC541MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC541N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Descriptions
Pin Names
OE1, OE2
I0 - I7
O0 - O7
Descriptions
3-STATE Output Enable Inputs
Inputs
3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS011639.prf
Truth Table
Inputs
OE1
L
H
X
L
H = HIGH Voltage Level
L = LOW Voltage Level
OE2
I
LH
XX
HX
LL
X = Immaterial
Z = High Impedance
Outputs
H
Z
Z
L
www.fairchildsemi.com
1 page  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
5 www.fairchildsemi.com
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| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet 74VHC541SJ.PDF ] | |
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