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PDF SDA9400 Data sheet ( Hoja de datos )
| Número de pieza | SDA9400 | |
| Descripción | Scan Rate Converter using Embedded DRAM Technology Units | |
| Fabricantes | ETC | |
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PRELIMINARY DATA SHEET
SDA 9400
SCARABAEUS
Scan Rate Converter
using Embedded
DRAM Technology Units
Edition Feb. 28, 2001
6251-551-1PD
1 page  
SDA 9400
1 General description
The SDA 9400 is a new component of the Micronas MEGAVISION® IC set in a 0.35 µm embedded
DRAM technology (frame memory embedded). The SDA 9400 is pin compatible to the SDA 9401
(field memory embedded). The SDA 9400 comprises all main functionalities of a digital featurebox
in one monolithic IC.
The scan rate conversion to 100/120 Hz interlaced (50/60 Hz progressive) is based on a motion
adaptive algorithm. The scan rate converted picture can be vertically expanded. The SDA 9400 has
a freerunning mode, therefore features like scan rate conversion to e.g. 70, 75 Hz with joint lines or
multiple picture display (e.g. tuner scan) are possible.
Due to the frame based signal processing, the noise reduction has been greatly improved.
Furthermore separate motion detectors for luminance and chrominance have been implemented.
For automatic controlling of the noise reduction parameters a noise measurement algorithm is
included, which measures the noise level in the picture or in the blanking period. In addition a spatial
noise reduction is implemented, which reduces the noise even in the case of motion. The input
signal can be compressed horizontally and vertically with a certain number of factors. Therefore split
screen is supported.
Beside these additional functions like coloured background, windowing and flashing are
implemented.
2 Features
• Two input data formats
- 4:2:2 luminance and chrominance parallel (2 x 8 wires)
- ITU-R 656 data format (8 wires)
• Two different representations of input chrominance data
- 2‘s complement code
- Positive dual code
• Flexible input sync controller
• Flexible compression of the input signal
- Digital vertical compression of the input signal (1.0, 1.25, 1.5, 1.75, 2.0, 3.0, 4.0)
- Digital horizontal compression of the input signal (1.0, 2.0, 4.0)
• Noise reduction
- Motion adaptive spatial and temporal noise reduction (3D-NR)
- Temporal noise reduction for luminance frame based or field based
- Temporal noise reduction for chrominance field based
- Separate motion detectors for luminance and chrominance
- Flexible programming of the temporal noise reduction parameters
- Automatic measurement of the noise level (5 bit value, readable by I²C bus)
• 3-D motion detection
- High performance motion detector for scan rate conversion
- Global motion detection flag (readable by I²C bus)
- Movie mode and phase detector (readable by I²C bus)
Micronas
5 Preliminary Data Sheet
5 Page 
SDA 9400
6 System description
6.1 Input sync controller (ISC)
Input signals
Signals
HIN
Pin number
23
VIN 22
SYNCEN
29
Description
horizontal synchronization signal (polarity
programmable, I²C bus parameter 01h
HINPOL, default: high active)
vertical synchronization signal (polarity
programmable, I²C bus parameter 01h
VINPOL, default: high active)
enable signal for HIN and VIN signal, low
active (see also Input format conversion
(IFC) on page 15)
The input sync controller derives framing signals from the H- and V-Sync for the input data
processing. The framing signals depend on different parameters and mark the active picture area.
Input parameter
HIN
VIN
lines
per
field
pixels per line
NALIP+PD
(VERPOS*2)
(ALPFIP*2)
(VERWIDTH*2)
(HORPOS* (HORWIDTH*32)*
32)*CLK1
CLK1
(NAPIPDL*4 +
NAPIPPH + PD)*
CLK1
(APPLIP*32)*CLK1
PD - Processing Delay
The distance between the incoming H-syncs in system clocks of clk1 must be even.
Micronas
11 Preliminary Data Sheet
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SDA9400.PDF ] | |
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