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PDF SDA9257 Data sheet ( Hoja de datos )
| Número de pieza | SDA9257 | |
| Descripción | Clock Sync Generator | |
| Fabricantes | Siemens | |
| Logotipo |  |
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Clock Sync Generator
SDA 9257
Preliminary Data
Features
q All settings made by I2C Bus
q PLL lock-in behavior can be set to TV- or VCR mode
q Automatic clamping of CVBS input
q Provides all horizontal and vertical sync signals and
clocks for operating PAMUX, analog color decoders,
the A/D converters, PSND and Featurebox
q Free-running capability
q Frequency generator function possible with digitally
adjustable frequency
P-DIP-28-1
q Lock-in function of the PLL on CVBS also possible
with externally supplied 24-MHz or 27-MHz clock
q Multi-standard operation (50 Hz, 60 Hz; PAL, NTSC, SECAM)
q Vertical noise suppression and 50/60-Hz detection
q Serial digital output for actual frequency value and CVBS-black level
Applications
q Memory based image improvement with analog color decoder
q Memory based image improvement with digital multi-standard decoder
q Free-running sync generator
q Digital frequency synthesizer
MOS IC
Type
SDA 9257
Ordering Code
Q67100-H5038
Package
P-DIP-28-1
Functional Description
The clock sync generator consists essentially of the following function blocks (refer to block
diagram):
q Analog clamping
q 7-bit, 27-MHz A/D converter
q Sync processor with digital horizontal PLL, vertical sync processor and pulse generator
q Clock generator with discrete timing oscillator, D/A converter, analog PLL and divider, as well as
a crystal oscillator
q I2C Bus interface
q Button flutter elimination
Semiconductor Group
182
01.94
1 page  
SDA 9257
Detailed Circuit Description
Description of I2C Interface
Slave Address:
B: Equal to the value set on pin ADR1
1 0 1 1 0 B C C: Equal to the value set on pin ADR0
Receiver Format:
S Slave Address
S: Start condition
A: Acknowledge
P: Stop condition
0A
Sub Address
A
Data Byte
AP
Semiconductor Group
186
5 Page 
SDA 9257
All times quoted below refer to a nominal frequency of 27 MHz on CLK1
BLN Start Time (subaddress 05)
BLN Start Time in Relation to
Reference Time (refer also to timing
diagram 1)
Time
9.62 µs
Number in 13.5-MHz
Clock Periods
+ 130
– (– 128) + 2*
... ...
Control Bits
± (Two’s Complement) (LSB)
BON8 BON7 BON6 … BON2 BON1
1 0 0…0 0
...
0.22 µs
0.15 µs
...
+3
+2
– (– 1) + 2*
– ( 0) + 2*
...
1 1 1…1 1
0 0 0…0 0
...
– 9.25 µs – 125
– (+ 127) + 2*
0
1
1…1
1
BLN Stop Time (subaddress 06)
BLN Stop Time in Relation to
Reference Time
Time
+ 0.22 µs
Number in 13.5-MHz
Clock Periods
+ 3 0 + 3*
... ...
+ 9.63 µs
+ 9.0 µs
+ 130
+ 131
...
127 + 3*
128 + 3*
+ 19.11 µs + 258
255 + 3*
Control Bits
(One’s Complement)
BOF8 BOF7 BOF6 … BOF2 BOF1
0 0 0…0 0
...
0 1 1…1 1
1 0 0…0 0
...
1 1 1…1 1
* Due to internal delays
Semiconductor Group
192
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SDA9257.PDF ] | |
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