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PDF SDA9251-2X Data sheet ( Hoja de datos )
| Número de pieza | SDA9251-2X | |
| Descripción | 868352-Bit Dynamic Sequential Access Memory for Television Applications (TV-SAM) | |
| Fabricantes | Siemens | |
| Logotipo |  |
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868352-Bit Dynamic Sequential Access Memory
for Television Applications (TV-SAM)
SDA 9251-2X
Preliminary Data
Features
q 212 x 64 x 16 x 4-bit organization
q Triple port architecture
q One 16 x 4-bit input shift register
q Two 16 x 4-bit output shift registers
q Shift registers independently and simultaneously
accessible
q Continuous data flow even at maximum speed
q 33-MHz shift rate - 0.27-Gbit/s total data rate
q All inputs and outputs TTL-compatible
q Tristate outputs
q Random access of groups of 16 x 4 bits for a wide range
of applications
q Refresh-free operation possible
q 5 V ± 10 % power supply
q 0 … 70 °C operating temperature range
q Low power dissipation: 550 mW active, 28 mW standby
q Suitable for all common TV standards
q Allows flicker and noise reduction simultaneously
with only one field memory
q Applications: TV, VCR, image processing,
video printers, data compressors, delay lines,
time base correctors, HDTV
P-DSO-28-.350
CMOS IC
Type
SDA 9251-2X
Ordering Code
Q67100-H5063
Package
P-DSO-28-.350 (SMD)
Semiconductor Group
159
01.94
1 page  
SDA 9251-2X
Typical Memory Cycle Sequence
A typical application of the TV-SAM is a real-time interfield image processing combined with flicker
reduction. This can be achieved, for example, by writing and reading with 13.5-MHz clock rate via
port C and B and by simultaneously reading port A with 27-MHz double speed clock. A main cycle
of 4 consecutive RE cycles of transfer is needed:
1st. RE-cycle: Read transfer from memory to latch A
2nd. RE-cycle: Read transfer from memory to latch B
3rd. RE-cycle: Same as 1st. RE cycle
4th. RE-cycle: Write transfer from latch C to memory
Each transfer cycle is preceeded by an address cycle as shown in the diagram page 164:
For the clock rates mentioned this means a serial cycle time of 74 ns at port B and C and 37 ns at
port A. The addressing cycle time for each port is given by 16 times the serial data rate. Thus we
have an addressing cycle time of approx. 1184 ns for port B and port C. The address for port A must
be loaded every 592 ns. Since all addresses are shifted in sequentially, a RE cycle time of approx.
296 ns is necessary.
The beginning of a block of 16 serial data at port A or B is determined by RA and RB, respectively.
The end of the serial input data block at port C is controlled by WT. Since RA, RB and WT can be
independently chosen (except for small forbidden time windows when memory transfers are
executed), the serial data streams can be shifted against each other without influencing the RE
cycles.
Semiconductor Group
163
5 Page 
SDA 9251-2X
DC Characteristics
VCC = 5 V ± 10 %; TA = 0 to 70 °C
Parameter
Symbol
Test enable input
high voltage
VIH (TF)
Limit Values
min. typ. max.
VCC +
4.5
10.5
Test disable input
low voltage
VIL (TF)
H-output voltage
VQH
L-output voltage
VQL
Input leakage current II (L)
Output leakage current IQ (L)
Average supply current ICCa
– 1.0
2.4
– 10
– 10
VCC +
1.0
0.4
10
10
100
Standby supply current ICCb
5
Unit
V
V
V
V
µA
µA
mA
mA
Test Condition
At normal operation the
pin TF has to be
connected to VIL (TF) level
or left unconnected.
See test enable input high
voltage
IOUT = – 2.5 mA
IOUT = 2.1 mA
0 V ≤ VI ≤ 6.5 V
OEA = OEB = VIH
(tSC port A = tSC min)
(tSC port B = 2 tSC min)
(tSC port C = 2 tSC min)
(tRC = tRC min)
ICCa depends on cycle rate
and on output loading.
Specified values are
measured with open
output.
(RE = OEA = OEB = VCC)
tSC (SCA, SCB, SCAD) =
max. (tSC)
Semiconductor Group
169
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet SDA9251-2X.PDF ] | |
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