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74VHC273MTC Datasheet دیتاشیت PDF دانلود

دیتاشیت - Fairchild Semiconductor - Octal D-Type Flip-Flop

شماره قطعه 74VHC273MTC
شرح مفصل Octal D-Type Flip-Flop
تولید کننده Fairchild Semiconductor 
آرم Fairchild Semiconductor 


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74VHC273MTC شرح
April 1994
Revised April 1999
74VHC273
Octal D-Type Flip-Flop
General Description
The VHC273 is an advanced high speed CMOS Octal D-
type flip-flop fabricated with silicon gate CMOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
The register has a common buffered Clock (CP) which is
fully edge-triggered. The state of each D input, one setup
time before the LOW-to-HIGH clock transition, is trans-
ferred to the corresponding flip-flop’s Q output. The Master
Reset (MR) input will clear all flip-flops simultaneously. All
outputs will be forced LOW independently of Clock or Data
inputs by a LOW voltage level on the MR input.
An input protection circuit insures that 0V to 7V can be
applied to the inputs pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s High Speed: fMAX= 165 MHz (typ) at VCC = 5V
s Low power dissipation: ICC = 4 µA (max) at TA = 25°C
s High noise immunity: VNIH = VNIL = 28% VCC (min)
s Power down protection is provided on all inputs
s Low noise: VOLP = 0.9V (max)
s Pin and function compatible with 74HC273
Ordering Code:
Order Number Package Number
Package Description
74VHC273M
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74VHC273SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC273MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC273N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0–D7
MR
CP
Q0–Q7
Description
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
© 1999 Fairchild Semiconductor Corporation DS011670.prf
www.fairchildsemi.com

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