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74VHC175 fiches techniques PDF

Fairchild Semiconductor - Quad D-Type Flip-Flop

Numéro de référence 74VHC175
Description Quad D-Type Flip-Flop
Fabricant Fairchild Semiconductor 
Logo Fairchild Semiconductor 





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74VHC175 fiche technique
August 1993
Revised April 1999
74VHC175
Quad D-Type Flip-Flop
General Description
The VHC175 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation.
The VHC175 is a high-speed quad D-type flip-flop. The
device is useful for general flip-flop requirements where
clock and clear inputs are common. The information on the
D inputs is stored during the LOW-to-HIGH clock transition.
Both true and complemented outputs of each flip-flop are
provided. A Master Reset input resets all flip-flops, inde-
pendent of the Clock or D inputs, when LOW.
An input protection circuit insures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s High Speed: fMAX = 210 MHz (typ) at VCC = 5V
s Low power dissipation: ICC = 4 µA (max) at TA = 25°C
s High noise immunity: VNIH = VNIL = 28% VCC (min)
s Power down protection is provided on all inputs
s Low noise: VOLP = 0.8V (max)
s Pin and function compatible with 74HC175
Ordering Code:
Order Number Package Number
Package Description
74VHC175M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74VHC175SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC175MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC175N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D0–D3
CP
MR
Q0–Q3
Q0–Q 3
Description
Data Inputs
Clock Pulse Input
Master Reset Input
True Outputs
Complement Outputs
Logic Symbols
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS011637.prf
www.fairchildsemi.com

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